NEC QB-V850ESFJ3 Preliminary User's Manual page 41

QB-V850ESFJ3 Preliminary User's Manual
• Cases in which two instructions are not simultaneously executed
In the following cases, two instructions are not simultaneously executed.
(a) If the first instruction is the first instruction after execution branches to an address that is not word
aligned.
Example
0x1006
0x1008
If a branch to address 0x1006 occurs, the two instructions are not executed simultaneously because
the first instruction is not word aligned (because the lower 1 byte of the address is not 0, 4, 8, A, or C).
(b) If the second instruction is sld and writing to the ep register is not completed.
Example
0x1004
0x1006
In this case, the value of r10 is written to the ep register by the mov instruction at address 0x1004.
However, the two instructions are not executed simultaneously because WB (writeback) of the mov
instruction is not completed when the sld.b instruction at address 0x1006 is executed.
(c) If the second instruction is bcc (conditional branch instruction) and a flag hazard occurs (the
instruction immediately before or the instruction before that instruction may update the flags).
Example
0x1004
0x1006
The bn instruction that references the S flag and branches must wait for execution of the cmp
instruction at address 0x1004 because the S flag is changed by the cmp instruction.
consequence, the bn instruction causes a flag hazard and the two instructions are not executed
simultaneously.
(d) If the second instruction is sld and both of the load buffers are in the WB wait status.
Example
Suppose that the following instructions are located in the memory.
0x1000
0x1002
0x1004 ld.w 0x3000[r10],r11
0x1008 ld.w 0x3004[r10],r12
0x100c mov r8,r9
0x100e sld.b 0x10[ep],r13
If ld.w at addresses 0x1004 and 0x1008 accesses the external memory, several clocks of wait states
are inserted. If the instruction at address 0x100e is executed, then the load buffer is in the "WB wait"
status because WB of the ld.w instructions at addresses 0x1004 and 0x1008 is not completed, and the
two instructions at address 0x100c and 0x100e are not simultaneously executed.
mov r10,r12
sld.b 0x8[ep],r11
mov r10,ep
sld.b 0x8[ep],r11
cmp r0,r10
bn 0xf0
nop
nop
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