Cirrus Logic CS2100-CP Manual

Features
Clock Multiplier / Jitter Reduction

– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to 30
MHz Clock Source
Highly Accurate PLL Multiplication Factor

– Maximum Error Less Than 1 PPM in High-
Resolution Mode
I²C / SPI™ Control Port

Configurable Auxiliary Output

Flexible Sourcing of Reference Clock

– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
Minimal Board Space Required

– No External Analog Loop-filter
Components
I²C/SPI
Software Control
8 MHz to 75 MHz
Low-Jitter Timing
Reference
50 Hz to 30 MHz
Frequency
Reference
http://www.cirrus.com
Fractional-N Clock Multiplier
I²C / SPI
Frequency Synthesizer
Digital PLL & Fractional
Output to Input
Clock Ratio
Cirrus Logic Confidential
Copyright  Cirrus Logic, Inc. 2009–2015
(All Rights Reserved)
General Description
The CS2100-CP is an extremely versatile system
clocking device that utilizes a programmable phase
lock loop. The CS2100-CP is based on a hybrid ana-
log-digital PLL architecture comprised of a unique
combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an exter-
nal noisy synchronization clock at frequencies as low
as 50 Hz. The CS2100-CP supports both I²C and SPI
for full software control.
The CS2100-CP is available in a 10-pin MSOP pack-
age in Commercial (-10°C to +70°C) and Automotive-
D (-40°C to +85°C) and Automotive-E (-40°C to
+105°C) grades. Customer development kits are also
available for device evaluation. Please see
Information" on page 32
3.3 V
Timing Reference
Frequency Reference
PLL Output
Lock Indicator
Fractional-N
N
N Logic
CS2100-CP
"Ordering
for complete details.
Auxiliary
Output
6 to 75 MHz
PLL Output
OCT '15
DS840F3