Cirrus Logic CS2000-OTP General Description Manual

Fractional-n clock synthesizer & clock multiplier
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Fractional-N Clock Synthesizer & Clock Multiplier
Features
Delta-Sigma Fractional-N Frequency Synthesis
Generates a Low Jitter 6 - 75 MHz Clock
from an 8 - 75 MHz Reference Clock
Clock Multiplier / Jitter Reduction
Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery 50 Hz to 30 MHz Clock
Source
Highly Accurate PLL Multiplication Factor
Maximum Error Less Than 1 PPM in High-
Resolution Mode
One-Time Programmability
Configurable Hardware Control Pins
Configurable Auxiliary Output
Flexible Sourcing of Reference Clock
External Oscillator or Clock Source
Supports Inexpensive Local Crystal
Minimal Board Space Required
No External Analog Loop-filter
Components
Hardware Control
8 MHz to 75 MHz
Low-Jitter Timing Reference
50 Hz to 30 MHz
Frequency Reference
http://www.cirrus.com
Hardware Configuration
Output to Input
Clock Ratio
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
Cirrus Logic Confidential
Copyright  Cirrus Logic, Inc. 2009–2015
(All Rights Reserved)

General Description

The CS2000-OTP is an extremely versatile system
clocking device that utilizes a programmable phase lock
loop. The CS2000-OTP is based on a hybrid analog-
digital PLL architecture comprised of a unique combina-
tion
of
a
Delta-Sigma
Synthesizer and a Digital PLL. This architecture allows
for both frequency synthesis/clock generation from a
stable reference clock as well as generation of a low-jit-
ter clock relative to an external noisy synchronization
clock with frequencies as low as 50 Hz. The CS2000-
OTP has many configuration options which are set once
prior to runtime. At runtime there are three hardware
configuration pins available for mode and feature
selection.
The CS2000-OTP is available in a 10-pin MSOP pack-
age in Commercial (-10°C to +70°C) and Automotive-D
(-40°C to +85°C) and Automotive-E (-40°C to +105°C)
grades. Customer development kits are also available
for custom device prototyping, small production pro-
gramming, and device evaluation. Please see
Information" on page 29
3.3 V
Timing Reference
Frequency Reference
PLL Output
Lock Indicator
Fractional-N
Frequency Synthesizer
N
CS2000-OTP
Fractional-N
Frequency
"Ordering
for complete details.
Auxiliary
Output
6 to 75 MHz
PLL Output
OCT '15
DS758F3

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Summary of Contents for Cirrus Logic CS2000-OTP

  • Page 1: General Description

    – Generates a Low Jitter 6 - 75 MHz Clock loop. The CS2000-OTP is based on a hybrid analog- from an 8 - 75 MHz Reference Clock digital PLL architecture comprised of a unique combina- Clock Multiplier / Jitter Reduction ...
  • Page 2: Table Of Contents

    CS2000-OTP TABLE OF CONTENTS 1. PIN DESCRIPTION ..........................4 2. TYPICAL CONNECTION DIAGRAM ..................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ..................6 RECOMMENDED OPERATING CONDITIONS ..................6 ABSOLUTE MAXIMUM RATINGS ......................6 DC ELECTRICAL CHARACTERISTICS ....................6 AC ELECTRICAL CHARACTERISTICS ....................7 PLL PERFORMANCE PLOTS .......................
  • Page 3 CS2000-OTP 6.3.2 Reference Clock Input Divider (RefClkDiv[1:0]) ..............24 6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) ..............24 6.3.4 Low-Frequency Ratio Configuration (LFRatioCfg) ..............24 6.3.5 M2 Pin Configuration (M2Config[2:0]) ................... 25 6.3.6 Clock Input Bandwidth (ClkIn_BW[2:0]) ................25 7.
  • Page 4: Pin Description

    CS2000-OTP 1. PIN DESCRIPTION CLK_OUT XTI/REF_CLK AUX_OUT CLK_IN Pin Name Pin Description Digital Power (Input) - Positive power supply for the digital and analog sections. Ground (Input) - Ground reference. CLK_OUT PLL Clock Output (Output) - PLL clock output. Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, AUX_OUT or a status signal, depending on configuration.
  • Page 5: Typical Connection Diagram

    CS2000-OTP 2. TYPICAL CONNECTION DIAGRAM +3.3 V 0.1 µF 1 µF System Microcontroller CS2000-OTP To circuitry which requires CLK_OUT Frequency Reference CLK_IN a low-jitter clock To other circuitry or XTI/REF_CLK AUX_OUT Microcontroller Low-Jitter REF_CLK Timing Reference N.C. Crystal 40 pF 40 pF Figure 1.
  • Page 6: Characteristics And Specifications

    CS2000-OTP 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note Parameters Symbol Units DC Power Supply (Note Ambient Operating Temperature (Power Applied) Commercial Grade °C Automotive-D Grade °C Automotive-E Grade +105 °C...
  • Page 7: Ac Electrical Characteristics

    CS2000-OTP AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T = -10°C to +70°C (Commercial Grade); = -40°C to +85°C (Automotive-D Grade); T = -40°C to +105°C (Automotive-E Grade); C = 15 pF.
  • Page 8: Pll Performance Plots

    CS2000-OTP PLL PERFORMANCE PLOTS Test Conditions (unless otherwise specified): VD = 3.3 V; T = 25 °C; C = 15 pF; f = 12.288 MHz; CLK_OUT = 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] = 11.
  • Page 9: Architecture Overview

    CS2000-OTP 4. ARCHITECTURE OVERVIEW Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2000 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu- tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to quickly tune to a new frequency.
  • Page 10: Fractional-N Source Selection For The Frequency Synthesizer

    CS2000-OTP Delta-Sigma Fractional-N Frequency Synthesizer Timing Reference Phase Internal Voltage Controlled PLL Output Clock Comparator Loop Filter Oscillator Fractional-N Divider Delta-Sigma Modulator Digital PLL and Fractional-N Logic Digital Filter Frequency Frequency Reference Comparator for Clock Frac-N Generation Output to Input Ratio for Hybrid mode Figure 6.
  • Page 11: Applications

    5. APPLICATIONS One Time Programmability The one time programmable (OTP) circuitry in the CS2000-OTP allows for pre-configuration of the device prior to use in a system. There are two types of parameters that are used for device pre-configuration: modal and global. The modal parameters are features which, when grouped together, create a modal configuration...
  • Page 12: Crystal Connections (Xti And Xto)

    CS2000-OTP example of how to determine the range of RefClk frequencies around 12 MHz to be used in order to achieve the lowest jitter PLL output at a frequency of 12.288 MHz is as follows:   where: CLK__OUT Jitter...
  • Page 13: Adjusting The Minimum Loop Bandwidth For Clk_In

    CS2000-OTP which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Char- acteristics” on page 5.3.1 Adjusting the Minimum Loop Bandwidth for CLK_IN The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128 Hz using the ClkIn_BW[2:0] global parameter.
  • Page 14: Output To Input Frequency Ratio Configuration

    CS2000-OTP While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] pa- rameter. Referenced Control Parameter Definition ClkIn_BW[2:0] .......“Clock Input Bandwidth (ClkIn_BW[2:0])”...
  • Page 15: Ratio Modifier (R-Mod)

    CS2000-OTP 5.4.3 Ratio Modifier (R-Mod) The Ratio Modifier is used to internally multiply/divide the currently addressed R (Ratio stored in the register space remain unchanged). The available options for R-Mod are summarized in Table 2 on page 15. R-Mod is enabled via the M2 pin in conjunction with the appropriate setting of the M2Config[2:0] global parameter (see Section 5.7.2 on page...
  • Page 16: Manual Fractional-N Source Selection For The Frequency Synthesizer

    Digital PLL and CLK_IN for Hybrid PLL Mode. When CLK_IN is not present, the device will use RefClk and the static ratio for Frequency Synthesizer Mode. After losing CLK_IN, the CS2000-OTP will wait for 2 SysClk cycles before switching to Sy-...
  • Page 17: Ratio Configuration Summary

    CS2000-OTP 5.4.6 Ratio Configuration Summary The R is the user defined ratio for which up to four different values (Ratio ) can be stored in the one time programmable memory. The M[1:0] pins or LockClk[1:0] modal parameter then select the user de- fined ratio to be used (depending on if static or dynamic ratio mode is to be used).
  • Page 18: Pll Clock Output

    CS2000-OTP PLL Clock Output The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the M2 pin when the M2Config[1:0] global parameter is set to either 000 or 010.
  • Page 19: Mode Pin Functionality

    CS2000-OTP Mode Pin Functionality 5.7.1 M1 and M0 Mode Pin Functionality M[1:0] determine the functional mode of the device and select both the default User Defined Ratio and the set of modal parameters. The modal parameters are RModSel[1:0], AuxOutSrc[1:0], LockClk[1:0], and FracNSrc.
  • Page 20: M2 Configured As Auto Fractional-N Source Selection Disable

    5.8.1 Output Switching The CS2000-OTP is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an output, changing the auxiliary output source between REF_CLK and CLK_OUT, changing between Frequency Synthesizer and Hybrid PLL Mode, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock period.
  • Page 21: Pll Unlock Conditions

    CS2000-OTP 5.8.2 PLL Unlock Conditions Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un- locked: •...
  • Page 22: Parameter Descriptions

    CS2000-OTP 6. PARAMETER DESCRIPTIONS As mentioned in Section 5.1 on page 11, there are two different kinds of parameter configuration sets, Modal and Global. These configuration sets, shown in Figure 17, can be programmed in the field using the CDK2000 or pre- programmed at the factory.
  • Page 23: Auxiliary Output Source Selection (Auxoutsrc[1:0])

    CS2000-OTP 6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) Selects the source of the AUX_OUT signal. AuxOutSrc[1:0] Auxiliary Output Source RefClk. CLK_IN. CLK_OUT. PLL Lock Status Indicator. “Auxiliary Output” on page 18 Application: When set to 11, the AuxLockCfg global parameter sets the polarity and driver type (“AUX PLL...
  • Page 24: Global Configuration Parameters

    CS2000-OTP Global Configuration Parameters 6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg) When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] modal parameter = ‘11’), this global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal.
  • Page 25: M2 Pin Configuration (M2Config[2:0])

    CS2000-OTP 6.3.5 M2 Pin Configuration (M2Config[2:0]) Controls which special function is mapped to the M2 pin M2Config[2:0] M2 pin function Disable CLK_OUT pin. Disable AUX_OUT pin. Disable CLK_OUT and AUX_OUT. RModSel[1:0] Modal Parameter Enable. Force Manual Fractional N Source Selection.
  • Page 26: Calculating The User Defined Ratio

    Defined Ratio. This section is for those who would like to know more about how the User Defined Ratio is calculated and stored. Most calculators do not interpret the fixed point binary representation which the CS2000-OTP uses to define the output to input clock ratio (see Section 5.4.1 on page...
  • Page 27: Programming Information

    CS2000-OTP 8. PROGRAMMING INFORMATION Field programming of the CS2000-OTP is achieved using the hardware and software tools included with the CDK2000. The software tools can be downloaded from www.cirrus.com for evaluation prior to ordering a CDK. The CDK2000 is designed with built-in features to ease the process of programming small quantities of devices for pro- totype and small production builds.
  • Page 28: Package Dimensions

    CS2000-OTP 9. PACKAGE DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note  END VIEW SEATING PLANE SIDE VIEW 1 2 3 TOP VIEW INCHES MILLIMETERS NOTE 0.0433 1.10 0.0059 0.15 0.0295 0.0374 0.75 0.95 0.0059 0.0118 0.15 0.30 4, 5 0.0031...
  • Page 29: 10.Ordering Information

    CS2000-OTP 10.ORDERING INFORMATION The CS2000-OTP is ordered as an un-programmed device. The CS2000-OTP can also be factory programmed for large quantity orders. Please see “Programming Information” on page 27 for more details. Product Description Package Temp Range Container Pb-Free Grade...
  • Page 30 All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of Cirrus.

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