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4-61 .
Also at thi s time pin 7 of ce nte r board coun ter U 10 goes
L
O to inhib it that sect ion
o
f the counter. Th e 11
bi ts o f t he co unter that are used are all
L
O now. Th e fi rst two co un ter sectio ns, Ul 6 and U22, co nt inue to co un t
until 256 co un ts (mic roseconds) later ,
J
4(5) is cloc k ed . Th e 11 used co un ter bits are again at α11 zeros and the
256 co unts
h
ave been lost to compensate
f
or the extra analog posit ive offset m ent i on ed prev iously.
4-62 .
INTEGR ATOR COUNT DO WN. The cloc king of U4(5) makes coun ter U 10 pin 7 HI again so the whole
coun te r can co un t at the 1 MHz rate un til the integrator retur ns to zero . Wh en
t
he in tegrator gets to zero, the
co mp arator sw itc h es state a n d the L RAMP ACTIVE line goes HL signalli ng the en d of
t
he co un tin g . Th e RAMP
ACTIVE 1
M
IC ROS ECO ND CLOC K .pulses now stop and the stat ic co unters co ntain the Α/D
o
u tpu t. Top board
U18 (2, 3, 6) and U9 (1, 2, 3) in s ur e that the last pulse is of suffi cient duration to pro perly c l oc k t he co unters.
Th e L RAMP AC TIVE line be in g HI also turns on FET Q7 (botto m board) whic h
c
lamps the i ntegrato r at +30
m
V. Th e -9 .5 V is st ill on th r u Q6 .
4-63 .
END O F CO NV ER SION . Du ring the l ast half of the 2048-n ιic rosecond fixed ti me in terva l , ce nte r board
fl ip -flo p Ul was reset at pin 2, wh ic h reset
U
6 (decoder
U
7 was blank ed dur ing thi s reset to p revent unwa nted
output
spikes).
All
the
even ts
m en tione d so
f
ar
are
always
co mp lete pr ior to
the
TM
PLUS
4750-MI CROS ECO ND S ed ge whi ch cloc ks ce n ter board Ul 4750 mic roseconds afte r P AC ER TIME
M
ARK
initiated the co nve rsion . U6 t h en comes o ff reset and starts co un tin g whi ch ge ne rates fi rst the
L
ATCH pu lse at
U7(6) to
l
atch the coun ters ou tpu t in to the
L
ATCHES (U 15, U21, U9) and then the EOC (end of co n vers i o n)
pulse of U7(8) whi ch resets the co un te rs, a nd flip -flops U2(10), U1(6),
U4(2),
and U4(6) thereby pre p a r i n g the
circuitry for anot her conve rsion cycle .
4-64 .
One s mall va riation 1ο
t
he cycle exists when the HALF -O U TPUT INHIBIT li ne is
L
O in dicating that only
one of the two outpu t bytes from the previous co nv ersion cycle has been pr od u ced .
U
nde r
t
h is condition, the
LATCH pu lse does not reach
t
he latch es and the cur re nt co nve rsion is not transferred to the latc hes .
4-65 .
NE GATIVE OV ERRANGE OPERATI ON. If the an a log inpu t vo ltage
i
s more negat ive than negative fu ll
scale then t h e i ntegrator gets bac k to zero during the extra offset subt r actio n and
t
he ce nter board U5(4) goes HL
Th e co un ters are then h e l d reset for the remainder of
t
he cycle and the d igital outpu t is clamp ed to negative fu ll
scale .
Sign bit is ta ken from Q outpu t so
i
s i nve r ted .
4-67 .
Output Sequencer (F igure 4-11).
10000000000 = neg fu ll scale = -1024
4-66 .
POSITIVE OVERR AN G E O PER AT IO N. If
t
he analog input voltage is more positive th an posi t ive fu ll
scale, then
t
he integrator will n ot get bac k to zero before the co unte rs overflow .
W
hen they try to overflow
U 10(15) goes HI whi c h inhibits add itional cloc k pulses to the co un te rs, the outpu ts then remai n at all ones
f
or
t
he re mainde r
o
f
t
he cyc le a n d t h e di gita l
o
utpu t is clamp ed to pos itive fu ll scale.
0 1 1 1 1 1 1 1 1 1 1 = pos fu ll scale = +1023
Section IV -
P
rin ciples of
O
peratio n
Model 59313 Α
Sign bit is ta ken fr om Q ou tpu t so is
i
nverted. (See Appendix IV for two's co mpleme nt conversion .)
4-68 .
In α normal
o
perating sequence the END O F CO NVER SION pulse r esets th e output sequ encer flip-flop
whi ch sets the L
S
ELECT 0 line
L
O which di r ects the byte selector circ uit to select the 3 most significant b its of
t
he 1 Ι
b
it Α to D CONVERTER
o
utpu t (t he ot he r 5 bits of the 8 bit byte are all tied to the
m
ost significa nt bit,
that is, the sign bit) . Also at thi s tim e the Η DATA READY line goes HI to signal the so ur ce
h
ands h ake circui t
th at t h e o utpu t is ready . As soon as the 59313Α
i
s
i
n the TLK mode the Η TALK 0 Ν ΑΤΝ line goes HI and this
first byte
i
s pl ace d on th e 8 DI O (data in/out) lines of the bus.
W
hen the bus li stener
h
as acce pted the byte t he
4- 23
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