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Th e RS T pulse clears :
C HANN EL
S
ELECTOR sect ion (no channel se lected)
O UTPUT
S
EQUENCER section (no output)
Α to D CONV ERTER sectio n (conve rte r cleared)
PAC ER section (no pace se l ecte d)
The REVER SE CHANNEL and the
L
SN mode a r e n ot cleared.
4-34 .
DE VICE CLE AR/UNIV ER SAL BUS CO MMAND. When the bus co ntroll e r pl aces the D CL co mmand on
the DATA IN lines (d urin g ΑΤΝ mo d e) an d t h e ΑΤΝ CLK pulse is ge nerated, then the IFR, R ST, and DCL +
P
OR pulses all occur (t he sa me as power on).
Th e DCL +
P
O R pulse clea rs only t h e RE VERS E CHANNEL.
4-35 .
INTERFACE C LE AR. When the bus controller pu lses the IFC ( in terf ace clea r) line
L
O, the IFR (i nterface
r
eset) pulse is ge n e rated .
The IFR pu lse clea rs the L LSN and L TLK lines of the ADDRESS DE CO DIN G section a n d the L
S
ERIAL
POLL
M
ODE lin e of the S ER V IC E RE Q UEST sect ion, i .e ., the IFR pu lse terminates the ΤLΚ, LSN, and S ERI AL
POLL modes .
4-36 .
CI RCUIT D E SC RIPTIO N.
Section IV - Prin cip les of
O
p erat i on
M odel 59313Α
4-37 .
Each
c
irc ui t
m
ay n ot be co nf i ned to one circ uit board,
h
owever, each
s
ignal line
h
as the sa m e pin numbe r
in each board connecto r, as shown on the sc hem at i c d i ag r am, Fi gu res 6-10, 6-11, and 6-12 .
4-38 .
H
ewlett-Packar d Interface Bu s (HP-113) IN/OUT Co nn ections.
4-39 .
Each of
t
he HP-ΙΒ 's 8 DIO (data in/out)
l
ines ca n transmi t data into or
o
ut of the 59313 Α Α to D
Conve rte r via the b us co nn ecto r (Fig u re 4-3) . Th e way one of these
l
ines does this
i
s shown in
F
ig ure 4-4 .
W
hen data is coming to
t
he 59313Α , the instrument mu st be in the
L
SN mode and the open-coll ecto r driver on
t he ce nte r pc board is floating . Th e cir cui try then responds only to the HDIS and LDIS data inpu t li nes.
W
h en
data is leaving
t
he 59313Α ,
t
he in strume nt mu st be in
t
he TALK mode with the cente r board dr i ver dr i v ing t h e
data line DI OS (data in/out but in this case out only), wh il e the inpu t circ ui try ignores the HDIS and LDIS lines .
4-40 .
Input Bu ffers ( Fig ure 4-5.) .
4-41 .
Each of the fo ur analog input channels starts wi th an operat ional amplifier co nnected in
t
he non-inverting
mode to p rese nt α hig h impedance to the input signals .
E
ac h amp lifier's ga in can be changed to one of four
di ffere nt levels by α jumper that changes the feedback resistor .
4-42 .
Th e GA IN and ZERO POTS co n trol
t
he comm on summing amplifi er (BOTTOM BOA RD U27), whi ch
follows th e inpu t b uffe r ampli fi ers. Th e ga in control is part of
t
he inpu t resistance
f
or U27 and thereby varies the
stage ga in . Th e ze ro co nt rol adds or su bt r acts α sm al l constant curre n t to th e summ i ng jun ctio n (v irtual groun d)
α[ U27 pi n 2 to make the zero off set correction .
W
hen the FET switch for the c hannel
i
s off (o p en), th e co n trols
h
ave no effect .
W
hen
t
he ph one plug is re moved fro m
o
ne o f the inpu t j ac k s, t h e switching co n tacts in the jack
conn ect th e input to the inte rn al cali b ration vo ltage .
4- 1 1
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