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TRANSMITTING TO
SYSTEM 1440
RESPONSES FROM
SYSTEM 1440
NOTE
16
generally, but not always accomplish this. If necessary, the ENABLE
FINISHED RESPONSE command is a handy way to get a response
when nothing more than indicating FIFO empty is desired. The most
likely situation to cause concern is down loading a set of voltages.
This is where programming in card increments is convenient. The
sequence of COUNT, WRITE, 16 voltages, ENABLE FINISHED
RESPONSE, will fit into the 2132 buffer twice. First send one block
of writes, then loop sending blocks followed by a wait for finished
response. This gives maximum throughput while maintaining hand-
shaking. Note that if this loop is to cross mainframes the mainframe
select command should be included.
The data received by System 1440 is buffered to a depth of 40 com-
mands. All mainframes receive all commands independently of whether
they are selected or not. Those units not selected will not act upon the
command. This means that consideration of the buffer depth does not
include mainframe selection. The depth of the buffer has been set to
accommodate the expected size of command bursts. For instance, in a
setup of multiple units a burst of status requests may be issued without
waiting for any response (buffer depth max. of 16). Since the size of the
2132 input and output buffers are also 40 there should be no difficulties
involved. If the buffer size is ignored and the computer manages to
overflow it any following commands will be lost.
Output from System 1440 to the 2132 is only generated in response to a
request. There is no spontaneous transmission. When requesting
information from 1440 the buffer size of the 2132 must be taken into
account. The count option in the commands to the 1445 can generate a
block response of up to 257 words. The demand and measured i.d.
responses have been included to assist in verifying that no data re-
sponses are lost. The suggested mode of operation is to limit the count
to 39 (39 channels + 1 i.d. word fills 2132). If this is not done the 2132
must be read out fast enough to prevent overflow. This might be a
reasonable approach if the LAM is used as an interrupt.
Due to timing differences between the HV4032A/M and the 1440 System
High Voltage Mainframes, it may be necessary to remove a 6.8 µf
capacitor located on the 2132 PC board for operation with the 1440
mainframe. Since the 1440 system controller can transfer data at a
higher rate of speed, the capacitor can be removed to allow the 2132 to
transfer data faster. When a 2132 is shipped with a 1440 system, the
capacitor is removed at the factory before shipment. If the 2132 is being
bought separately for use with a 1440 System, it will be necessary to
remove the capacitor. This 6.8 µf capacitor is located in the top right-
hand corner of the PC board, between IC "BA" (7402) and IC "CA"
(74LS123). On the schematic it is designated "C9" and can be located on
sheet 4 of 7. The capacitor should be either de-soldered and removed
from the PC board or clipped out with a pair of wire cutters. This capaci-
tor should always be in place when the 2132 is used with the
HV4032A/M mainframe.
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