LeCroy 2132 Operator's Manual page 12

Eighteen data bits are transferred, two of which are used as LAM Status
Bits only on transmission to the 2132. Data transfer from the 2132 to the
HV mainframes is considerably slower than the corresponding response
communication. Because of the computer error checking (parity, framing,
etc.) the HV mainframe requires approximately 100 msec between
characters, making the total transfer time approximately 250 msec/word.
This timing is controlled by hardware within the 2132.
Responses are transmitted at the rate of 15 msec/word. THUS, TRANS-
MISSION OF 32 VOLTAGE SETTINGS REQUIRES APPROXIMATELY
SIX (6) SECONDS. In contrast, reading back 32 voltages can be accom-
modated in 500 msec.
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