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Appendix B
Specifications
Output impedance:
Settling time:
Slew rate:
Linearity error:
Output ranges:
External Trigger
Trigger mode:
Trigger threshold:
Hysteresis:
Input impedance:
Maximum input voltage:
Minimum event time:
Microprocessor and Data Communication
Processor:
Memory:
Data communication:
Expansion Ports
2
I
C expansion port:
Digital output:
Digital input:
0.5 Ω typical
10 μs (to 1% of FSR)
6 V/μs
±4 LSB
±200 mV to ±10 V full scale in six steps:
Range
Resolution
±10 V
312.5 μV
±5 V
156.25 μV
±2 V
62.5 μV
±1 V
31.25 μV
±500 mV
15.625 μV
±200 mV
6.25 μV
TTL level (isolated) or contact closure (non-
isolated), software selectable.
+1.3 V (rising edge), +1.1 V (falling edge)
0.3 V
50 kΩ
±12 V
5 μs
PowerPC 405GPr @ 240 MHz
16 MB SDRAM
USB 2.0
Power and control bus for front-end units.
Supports a number of front-ends equal to the
number of PowerLab analog inputs. Interface
communications rate of up to 10 Kbits/s.
8 independent lines, TTL output level
(8 mA maximum load per line)
8 independent lines, TTL input level,
threshold 1.2 V, 10 kΩ input impedance, 5 V
maximum
37
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