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Z490 Taichi
DRAM Voltage
Use this to configure DRAM Voltage. The default value is [Auto].
DRAM Activating Power Supply
Configure the voltage for the DRAM Activating Power Supply.
PCH Voltage
Configure the chipset voltage (1.0V).
VCCSFR Voltage
Configure the voltage for the VCCSFR.
VCCIO Voltage
Configure the voltage for the VCCIO.
VCCSTG Voltage
Configure the voltage for the VCCTG.
PLL Voltage Configuration
CPU Internal PLL Voltage
Default is 0.900V. Each step is 0.0175V. Adding 9~15 steps will help CPU PLL to
lock internal clock during High frequency under Ln2 cooling. For Example: 1.0575V
~ 1.1625V will be proper value. But the voltage level will be different on each
processor. User has to find the best value for your own processor. VCCPLL Voltage
must be at least 150mV higher than the target PLL voltage, or your system will hang.
GT PLL Voltage
Default is 0.900V. Each step is 0.0175V. Adding 9~15 steps will help CPU PLL to
lock internal clock during High frequency under Ln2 cooling. For Example: 1.0575V
~ 1.1625V will be proper value. But the voltage level will be different on each
processor. User has to find the best value for your own processor. VCCPLL Voltage
must be at least 150mV higher than the target PLL voltage, or your system will hang.
Ring PLL Voltage
Default is 0.900V. Each step is 0.0175V. Adding 9~15 steps will help CPU PLL to
lock internal clock during High frequency under Ln2 cooling. For Example: 1.0575V
~ 1.1625V will be proper value. But the voltage level will be different on each
processor. User has to find the best value for your own processor. VCCPLL Voltage
must be at least 150mV higher than the target PLL voltage, or your system will hang.
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