Sony Glasstron Lite PLM-A35E Service Manual page 48

Pin No. Pin Name
VSS
56
SEG07 to SEG00
57 to 64
V3 to V0
65 to 68
COM0 to COM3
69 to 72
SYNC DET
73
P81
74
DATA TO MASTER
75
DATA TO SLAVE
76
MODECON SCK
77
CS LCD
78
DD MAIN
79
P87
80
AVSS
81
BRIGHT A/D
82
83, 84 P91, P92
BATT SENCE
85
86 to 89 P94 to P97
AVCC
90
CS EEPROM
91
92 WE EEPROM
CS DA
93
PA3
94
LANC IN
95
LANC OUT
96
BUZZER
97
98 BACK UP VCC
CL1
99
CL0
100
Confidential
PLM-A35E (AEP)
I/O
—
Ground terminal
O
LCD segment drive signal output terminal Not used (open)
I
Bias voltage input for the LCD drive Not used
O
LCD common drive signal output terminal Not used (open)
I
Input terminal of check signal whether sync signal is present or not
—
Not used (open)
I
Serial data input from the EEPROM (IC302)
Serial data output to the EEPROM (IC302), LCD timing generator (IC801), and D/A
O
converter (IC804)
Serial data transfer clock signal output to the EEPROM (IC302), LCD timing generator
O
(IC801), and D/A converter (IC804)
O
Chip select signal output to the LCD timing generator (IC801)
O
Main power supply control signal output to the DC/DC converter (IC101)
—
Not used (open)
—
Ground terminal (for A/D input)
I
Brightness control (RV301) input terminal
— Not used (open)
I
Input of battery capacity detection when rechargeable battery is used (A/D input)
—
Not used (open)
—
Power supply terminal (+5V) (for A/D input)
O
Chip select signal output to the EEPROM (IC302)
O Data write enable signal output to the EEPROM (IC302)
O
Chip select signal output to the D/A converter (IC804)
—
Not used (open)
I
LANC serial data input terminal (for check)
O
LANC serial data output terminal (for check)
O
Buzzer sound output terminal Not used (open)
— Power supply terminal (+5V)
O
Sub system clock output terminal (32.768 kHz)
I
Sub system clock input terminal (32.768 kHz)
Description
4-42
Not used (open)