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7.8.
TG/CDS SCHEMATIC DIAGRAM
G
F
E
D
C
TO REG
TO REG
B
TO CPU
A
1
TO CCD
CN5301
0 1 MAIN (TG/CDS)
CN22
H1
H2
V4
V3
V2
V1
GND
GND
GND
CCD_OUT
CCD_HV
SUB
C5218
CCD_LV
RG
R5217
L5201
REG_3.2V
47
REG_15V
REG-8-5V
C5201
GND
CDS_CS
SCK3
SO3
CCD_SCS
DSGAT
NOTES : 1. The parts with marked ( ) is not used.
2. For TG/CDS waveforms, please refer to "WAVEFORM TABLE".
2
CCD
C5231
NC
NC
VM
V2
V4
V1
VH
C5230
C5229
V3
0.1
1
/25
SUB
VL
TESTEN
NC
100k
NC
NC
NC NC
L5203
22
L5202
22
T
C5219
C5221
6.8
/16
1
/16
3
NC
CCDCKH
IC5202
JCY0098
TG+V_DRIVER
4
5
CCD
VICK
NC
NC
C5237
10p
CLDCLK
VDD1
C5225
0.1
CK
VSS1
PBLK
CLPDM
NC
OBCLP
ID
WEN
NC
CKINH
6
28
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