Edp Port (Cn43) - Asus AAEON GENE-APL7 User Manual

2.6.21

eDP Port (CN43)

Note 1: LCD_PWR can be set to +3.3V or +5V by configuring JP2 for eDP Port. Driving
current supports up to 1A.
Note 2: +VCC_BKLT_eDP can be set to +5V or +12V by configuring JP2 for eDP Port.
Driving current supports up to 2A.
Pin Pin Name
1 LCD_PWR
2 LCD_PWR
3 GND
4 GND
5 EDP_TX2_N
6 EDP_TX2_P
7 GND
8 EDP_TX1_N
9 EDP_TX1_P
10 GND
11 EDP_TX0_N
12 EDP_TX0_P
13 GND
14 EDP_TX3_N
15 EDP_TX3_P
16 GND
17 EDP_AUXN
18 EDP_AUXP
19 GND
Chapter 2 – Hardware Information
Signal Type
PWR
PWR
GND
GND
DIFF
DIFF
GND
GND
GND
GND
GND
Signal Level
+3.3V/+5V
+3.3V/+5V
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