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the external memory devices, U705 has 1k of RAM and
512 bytes of EEPROM on chip. Miscellaneous logic and
switching functions are provided by U703, U709, and
U711.
Since the controller is the central interface between
the various subsystems of the radio, and because of the
controllers complexity, this section will be divided into
two areas of discussion, the microcomputer and its
associated circuits, and the controller board's circuit
operation.
A. Microprocessor (U705) and Associated Circuits
1. Functions
The microprocessor, in conjunction with the SLIC
gate array (U710) (which can actually be considered
an extension of the microprocessor), has two basic
functions: interfacing to the outside world and con-
trolling the internal workings of the radio. The
microprocessor interfaces directly to the keypad,
display, side buttons, PTT, rotary switch, battery
voltage indicator, toggle switch, and 13-pin univer-
sal connector. The microprocessor constantly
monitors these inputs and interprets any changes
into commands that control the rest of the radio.
Some control functions it performs include loading
the synthesizer with the desired RF frequency, turn-
ing the RF PA on or off, turning the microphone and
speaker on or off, enabling and disabling audio and
data paths, and generating tones. Operations and
operating conditions within the radio are interpreted
by the microprocessor and fed back to the operator
as visible (the display) or audible (alert tone) indica-
tions of current status.
2. Normal Operation
The regulated 5V output from U708 powers the
microprocessor (U705) and the rest of the digital
ICs. The controller's clock is generated by the ASF
IC, U701, which has a built in programmable clock
synthesizer.
3. Clock Synthesizer
Upon power-up, and assuming that the ASF IC
receives a proper 2.1MHz input on U701-E1 (which
comes from the transceiver board), the ASF IC out-
puts a 3.6864MHz CMOS square wave (0-5Vpp
logic) on U701-D1, which connects to the EXTAL
input of the microprocessor, U705-A6. The micro-
processor operates at 1/4 of this frequency, which in
this case computes to 921.6 kHz. In particular, the E
clock output (pin U705-A5) will be a 50% duty cycle
square wave at this frequency, and will control all
bus timing accesses. The clock signal is also rout-
ed to the SLIC (U710-A4).
After initialization, and upon power-up, the micro-
processor reprograms the ASF IC to change the
E-clock to either 1.8432MHz or 3.6864MHz. There-
22
fore, soon after the controller is powered up, serial
data is being sent to the ASF IC on signal lines
U701-E3 and U701-F1. The ASF IC select line
U701-F2 is held low, and the UP CLK signal from
U701-D1 should be 4 x 1.8432MHz (=7.3728MHz)
or 4 x 3.6864MHz (=14.7456MHz), and the ECLK
signal is 1.8432MHz or 3.6864MHz.
4. Bus Operation
The microprocessor operates in expanded memory
mode and executes firmware contained in memory,
U715. The microprocessor uses a non-multiplexed
address data bus, consisting of data lines D0 thru
D7 and address lines A0 thru A15. In addition, the
microprocessor has integrated chip-select logic so
that external memories can be accessed without the
need for external address decoder gates. These
chip-select signals are provided by pins U705-PG5,
PG6, and PG7.
The SLIC (U710) provides an extra 32 I/O ports
which can be accessed as byte-wide memory loca-
tions. These ports are used to generate additional
control signals or to read more input signals.
In addition, the SLIC also provides a memory-
management function (MMU). Since the micropro-
cessor only provides 16 address lines, it can only
directly address 64K (= 2 16 ) of external memory.
The SLIC contains logic to switch in 16K blocks of
Flash memory, so that larger address space can be
realized.
When the controller board is functioning normally,
the microprocessor's address and data lines should
be toggling at CMOS logic levels. Specifically, the
logic-high levels should be between 4.8 and 5.0V,
and the logic-low levels should be between 0 and
0.2 V. No other intermediate levels should be
observed, and the rise and fall times should be < 30
nsec. The low-order address lines (A0-A4) and the
data lines (D0-D7) should be toggling at a high rate;
e.g., you should set your oscilloscope sweep to 1
µsec/div or faster to observe individual pulses. High-
speed CMOS transitions should also be observed
on the microprocessor control lines such as R/W*
(U705-B6), and the chip-select lines U705-PG7,
PG6, and PG5. Another line of interest is the MODA
line, pin U705-C5, which is also connected to U703
pin 1 and R727. While the CPU is running, this sig-
nal is an open-drain CMOS output which goes low
whenever the µC begins a new instruction (an
instruction typically requires 2-4 external bus cycles,
or memory fetches). Since it is an open-drain out-
put, however, the waveform rise assumes an
exponential shape similar to an RC circuit.
On the microprocessor (U705), the lines XIRQ (pin
E8) and RESET (pin E5) should be high during nor-
mal operation. Whenever a data or address line
becomes open or shorted to an adjacent line, a
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Troubleshooting
