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System Management Bus Header
A System Management Bus header for additional slave devices or sensors is located at
JSMB1. See the table below for pin definitions.
Nano SIM Slot
The JSIM1 slot supports a Nano SIM card.
LED2
UID
C
MH6
C
A
JSXB1A
LED3
LAN 2/3/4/5/6/7/8/9
LEDM1
C
A
1
JBM1
JVGA1
COM2
JMD1_SRW1
JMD2_SRW1
JSIM1
2
JPL2:
LAN 2/3/4/5
1-2:ENABLE
2-3:DISABLE
JPL3:
LAN 6/7/8/9
1-2:ENABLE
2-3:DISABLE
JMD2:M.2-H
PCI-E 3.0 X2 / S-SATA4
JSXB1C
MH2
JNVI2C1
MH7
USB 0/1
USB 2/3
S-SATA3
JF1
S-SATA2
JPW1
MH4
JBT1
LED1
SMBus Header
Pin Definitions
Pin#
Definition
1
Data
2
Ground
3
Clock
PRESS FIT
COM1
USB 4/5
LAN 1
IPMI_LAN
LAN 10/11
JSDP3
JTGLED2
LAN 12/13
J1
JMD3:M.2-P
PCI-E 3.0 X1
JMD3_SRW1
JMD1: M.2-H
PCI-E 3.0 X4 / I-SATA4
BAR CODE
DESIGNED IN USA
X11SDW-4C-TP13F
REV:1.01
CPU
JF1:
PWR
OH
HDD
PWR
RST X
NIC2
NIC1
ON
FF
LED
LED
JD1:
JPT1:TPM
1-3:PWR LED
1-2:ENABLE
4-7:SPEAKER
2-3:DISABLE
BT1
FAN4
FAN3
47
1. SMBus Header
JBM2
2. Nano SIM Slot
MH3
JPL1
JPI2C1
JLANLED1
JTGLED1
JL1
MH5
JSTBY1
MH1
Chapter 2: Installation
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