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8.7
Diagram
SSB v1: Class-D
Block Diagram
Shutdown
Control
Pin Configuration
NAME
SD
RIN
LIN
GAIN0
GAIN1
MUTE
BSL
PVCCL
LOUT
PGNDL
VCLAMP
BSR
ROUT
PGNDR
PVCCR
AGND
AGND
BYPASS
AVCC
Thermal pad
B06A, TPA3123D (IC 7L10)
1 F
LIN
RIN
1 F
1 F
BYPASS
AGND
AVCC
SD
MUTE
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
TERMINAL
I/O/P
24-PIN
(PWP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
2
I
AVCC
6
I
Audio input for right channel
5
I
Audio input for left channel
18
I
Gain select least-significant bit. TTL logic levels with compliance to AVCC
17
I
Gain select most-significant bit. TTL logic levels with compliance to AVCC
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =
4
I
outputs enabled). TTL logic levels with compliance to AVCC
21
I/O
Bootstrap I/O for left channel
1, 3
P
Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
22
O
Class-D 1/2-H-bridge positive output for left channel
23, 24
P
Power ground for left-channel H-bridge
11
P
Internally generated voltage supply for bootstrap capacitors
16
I/O
Bootstrap I/O for right channel
15
O
Class-D 1/2-H-bridge negative output for right channel
13, 14
P
Power ground for right-channel H-bridge.
10, 12
P
Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
9
P
Analog ground for digital/analog cells in core
8
P
Analog ground for analog cells in core
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
7
O
external capacitor sizing.
19, 20
P
High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Connect to ground. Thermal pad should be soldered down on all applications to properly
Die pad
P
secure device to printed wiring board.
Figure 8-7 Internal block diagram and pin configuration
IC Data Sheets
0.22 F
BSR
22 H
ROUT
0.68 F
PGNDR
0.68 F
PGNDL
LOUT
22 H
BSL
0.22 F
PVCCL
PVCCR
VCLAMP
1 F
GAIN0
GAIN1
1
24
PGNDL
2
23
PGNDL
3
22
LOUT
4
21
BSL
5
20
AVCC
6
19
AVCC
7
18
GAIN0
8
17
GAIN1
9
16
BSR
10
15
ROUT
PGNDR
11
14
12
13
PGNDR
DESCRIPTION
Q543.1E LA
8.
470 F
470 F
}
Control
18440_302_090303.eps
090303
EN 53
2009-Nov-20
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