Philips 32PFL3904H/12 Service Manual page 43

7.6.1 Video Subsystem
Refer to Figure 7-10 for the main video interfaces for the
PNX8543 and the video signal flow between blocks and
memory.
LOW IF
CVBS
RGB
YPbPr
VGA
Dual HDMI
DV (including
ITU-656)
TS
PCMCIA
TSDO
TSDI
CMD
The Video Subsystem consist of the following blocks:
• Analogue Front-End (AFE) block
• Video and PC Capture (VPC/PC) pipe
• HDMI Receiver interface
• Memory-Based Video Processor MBVP)
• Video Composition Pipe (CPIPE)
• Memory Based Video Processor (MBVP) VO-1
• Memory Based Video Processor (MBVP) VO-2
• Video Composition Pipe (CPIPE)
• Dual Flat Panel Display-LVDS (FPD-LVDS)
• Digital Encoder (DENC)
• Digital Video VIP
• 2D graphics block.
PNX8543x
A
VCP/PC
VCP_RX
AFE
(ADC)
PC_RX
HDMI
HDMI_
HDMI_UIP
RX
MBVP_
L2VO2
VIP
(ITU-656)
TSI
CAI
VMSP
Figure 7-10 PNX8543 video flow diagram
Circuit Descriptions
DDR2-SDRAM
MCU-DDR
2D_DE
VCP_
UIP
GFX1
VCP_
GFX2
WIFD
PIP
PC_
UIP
main
MBVP_
L2QTV
MBVP_
L2VO1
CPIPE_
L2VO
MSVD
Q543.1E LA
CPIPE_
LVDS_BUF
L2QTV
LVDS_TX
DAC
CVBS/Y
DENC
C
MUX DAC
A
7. EN 43
LCD panel
FPD-LVDS1
LCD panel
FPD-LVDS2
monitor
CVBS1/Y
monitor
CVBS2/C
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2009-Nov-20