Si5383/84 Reference Manual
Overview
This Reference Manual is intended to provide system, PCB design, signal integrity,
and software engineers the necessary technical information to successfully use the
Si5383/84 devices in end applications. The official device specifications can be found in
the Si5383/84 data sheet.
The Si5383/84 combines the industry's smallest footprint and lowest power network
synchronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter.
The three independent DSPLLs are individually configurable as a SyncE PLL or a gener-
al-purpose PLL for processor/FPGA clocking, and support digitally controlled oscillator
(DCO) mode for IEEE 1588 (PTP) clock steering applications. In addition, locking to
a 1 pps input frequency is available on DSPLL D. The DCO mode provides precise
timing adjustment to 1 part per trillion (ppt). The Si5383/84 can also be used in legacy
SETS systems needing Stratum 3/3E compliance. The unique design of the Si5383/84
allows the device to accept a TCXO/OCXO with any frequency, and the reference clock
jitter does not degrade output performance. The Si5383/84 is configurable via a serial
interface with in-circuit programmable non-volatile memory so it always powers up into
a known configuration. Programming the Si5383/84 is easy with ClockBuilder Pro soft-
ware. Factory pre-programmed devices are also available.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 9, 2021
RELATED DOCUMENTS
• Si5383/84 Data Sheet
• Si5383/84 Device Errata
• Si5383-EVB User Guide
• Si5383-EVB Schematics, BOM & Layout
• IBIS models
• To download support files, go to:
16. Accessing Design and Support
Collateral
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