REFERENCE MANUAL
Si5361/62/63 Reference Manual
Description
This Family Reference Manual is intended to provide
hardware, system, and software engineers the
necessary technical information to successfully use the
Si5361/62/63 in end applications. The official device
specifications and ordering information can be found
in the Si5361/62/63 data sheet.
The Si5361/62/63 jitter attenuating clock multipliers
combine fifth-generation DSPLL and MultiSynth™
technologies to enable any-frequency clock genera-
tion. These parts are used for applications that require
the highest level of jitter performance. The Si5361,
Si5362, and Si5363 are 1-DSPLL, 2-DSPLL, and 3-DSPLL
devices, respectively. These devices are programmable
with a serial interface. Alternatively, on-chip, program-
mable, non-volatile memory (NVM) can be used to
ensure power-up with known frequency configura-
tions.
Free-run, synchronous, and holdover modes of
operation are supported offering both automatic and
manual input clock switching. The loop filter is fully
integrated on-chip eliminating the risk of potential
noise coupling associated with discrete solutions.
Furthermore, the jitter attenuation bandwidth is digi-
tally programmable providing jitter performance opti-
mization at the application level. These devices can
generate any combination of output frequencies from
any input frequency within the specified input and
output range.
The Si5361/62/63 is programmed using Skyworks
ClockBuilder Pro software and can be made to power
up with known frequencies as a factory programmed
custom part or can be ordered as a "custom blank"
part for increased flexibility.
Skyworks Solutions, Inc. • Phone [949] 231-3000 • sales@skyworksinc.com • www.skyworksinc.com
206420B • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change without Notice
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Related Documents
•
Si5361/62/63 Data Sheet
•
UG514: Si536x-EVB User Guide
•
Si55xx, Si540x, and Si536x Recommended XTAL,
XO, VCXO, TCXO, and OCXO Reference Manual
•
AN1357: Si5360/61/62/63 Schematic Design and
Board Layout Guidelines
•
AN1360: Serial Communications and API Program-
ming Guide for Si536x, Si540x,and Si55xx Devices
March 21, 2023
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