Configuring The Aes/Ebu Outputs - Mutec iD Operating Manual

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A N H A N G
A N H A N G
A N H A N G
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WORDCLK
(setting)
WORD CLOCK This setting means that the rate is output as set.
SUPERCLK
(setting)
The SUPER CLOCK function is available for Word Clock rates of 44.1 or
48 kHz only. It is used for a rate adaptation required for Digidesign Pro-
Tools™ systems (not! ProTools HD™). Accordingly, the 44.1 kHz and 48 kHz
rates are available twice for selection: for both the WORDCLK and the
SUPERCLK, for ProTools™ systems, settings.
LEVEL / TERM
(function)
LEVEL / TERMINATION This function allows for adjusting the Word Clock
signal level of the selected output pair and for entirely disabling the
output. The page always displays the output level and the corresponding
internal termination of the output pair. The factory default is 2.6 V/75 R.
2.5 V / 75 R
(setting)
With this setting, the Word Clock signal is output with a level of 2.6 V and
an internal termination of 75 Ω.
3.5 V / 22 R
(setting)
With this setting, the Word Clock signal is output with a level of 3.5 V and
an internal termination of 22 Ω. This setting is recommended for Word
Clock signals to be transmitted over great distances.
SC adapted
(setting)
SUPER CLOCK adapted This is no adjustable setting but a status message
used only for clock rates set to Super Clock. Here, the level cannot be modi-
fied but only be disabled if required (OFF).

Configuring the AES/EBU Outputs

The two AES/EBU outputs can be set to various clock rates. In addition, two
important channel-status bits can be modified.
A E S F R E Q
|
4 4 . 1 k
AES/EBU outputs page
FREQ
(function)
FREQUENCY Sets the clock rate of the AES/EBU output pair. A so-called
AES/EBU clear-frame signal (compliant to AES 11-1997/2003) is generated.
The factory default is 44.1kHz.
16.0...192.0kHz
Altogether twelve different clock rates between 16.0...192.0 kHz can be
selected for the AES/EBU output pair, dependent on an external reference
or i nternally adjusted basis clock rate. Refer to the »Synchronizable and
Generatable Clock Rates« section in the appendix for a full list of all clock
rates.
DIST
(setting)
DISTRIBUTION This setting allows for forwarding an input AES/EBU or
S/PDIF clock signal to the AES/EBU outputs using a hardware bypass. As no
adjustments can be made in this mode, the other functions and parameters
will be hidden. The parameters and functions can only be accessed after the
internal AES/EBU generator has been enabled by selecting a different clock
rate.
In this mode, the synthesizer synchronizes to the input AES/EBU or S/PDIF
signal. Thus, all audio clock signals provided at the other outputs are linked
with phase lock to the input signal.
OFF
(setting)
OFF disables the AES/EBU outputs if not needed.
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W O R D L
2 4 B I T
(setting)
Due to the internal signal phase corrections
the synthesizer can re-lock temporarily
when switching AES/EBU clock frequencies.
F O R M A T
This does not affect the output signals or
P R O F
functionality of iD.
Example
An externally applied reference clock of
48.0k forces the AES/EBU outputs to clock
rates with a basis rate of 48.0k - whereas an
individually adjusted multiplier and divider
is furthermore active!
Input clock rate:
AES/EBU outputs: 96.0k
After an input reference change:
Input clock rate:
AES/EBU outputs: 88.2k
DIST does not provide redundancy for the
AES/EBU outputs. If the external AES/EBU
or S/PDIF clock source fails, the AES/EBU
outputs will fail, too!
During DISTRIBUTOR operation,
!
AES/EBU rates are set dependently
of externally applied clocks!
48.0k
44.1k
88
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