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IC3401
(VENUS ENGINE)
E LCD RST
GPIO14 N3
S LCDEVF DO
GPIO264 Y23
S LCD CS
GPIO256 U25
S LCDEVF SCK
GPIO262 W23
S LCDEVF DI
GPIO263 Y24
S EVF CS
GPIO257 V25
E EVF RST
GPIO42 H2
PANEL LVDSCKP
LVDS TXCP Y1
PANEL LVDSCKN
LVDS TXCM Y2
PANEL LVDSD2P
LVDS TX2P AA3
PANEL LVDSD2N
LVDS TX2M AA4
PANEL LVDSD1P
LVDS TX1P AA1
PANEL LVDSD1N
LVDS TX1M AA2
PANEL LVDSD0P
LVDS TX0P Y3
PANEL LVDSD0N
LVDS TX0M Y4
CH3103
CLK B1
GPIO45 G1
CH3102
CLK LR1
GPIO48 G4
CH3101
AODAT0
GPIO46 G2
FPGA INT
GPIO21 L2
PW FPG1.8V
FPGA PROGRAM
GPIO52 A8
FPGA INIT
GPIO54 C8
FPGA DONE
GPIO53 B8
CH3125
S FPGA CLK
GPIO56 C9
CH3124
S FPGA DO
GPIO58 A7
CH3123
S FPGA DI
GPIO57 D9
CH3122
S FPGA CS
GPIO59 B7
E FPGA RST
GPIO55 D8
CLK149 M SDI
GPIO384 AG9
GPIO368
AG10
BUS74 M SDIY0-9
GPIO392 AG7
GPIO395
AD7
BUS74 M SDIC0-9
GPIO402 AE5
VSYNC RST
GPIO240 U23
IC3501
(VENUS ENGINE)
VSYNC RST
GPIO239 U21
CLK149 S SDI
GPIO384 AG9
GPIO385
AF9
BUS74 S SDIY2-9
GPIO392 AG7
GPIO395
AD7
BUS74 S SDIC2-9
GPIO402 AE5
IC3101
(FPGA)
N3
IO L12P T1 MRCC 35
P3
IO L12N T1 MRCC 35
LCD LVDS0P
IO L10P T1 D14 14 P19
M2
IO L9P T1 DQS AD7P 35
LCD LVDS0N
IO L10N T1 D15 14
R19
M1
IO L9N T1 DQS AD7N 35
N2
IO L10P T1 AD15P 35
IO L10N T1 AD15N 35
N1
LCD LVDS1P
IO L11P T1 SRCC 14
M18
L3
IO L8P T1 AD14P 35
LCD LVDS1N
IO L11N T1 SRCC 14
M19
M3
IO L8N T1 AD14N 35
C16
IO L13P T2 MRCC 16
LCD LVDSCKP
IO L14P T2 SRCC 14
P18
LCD LVDSCKN
C17
IO L14P T2 SRCC 16
IO L14N T2 SRCC 14
R18
B18
IO L19P T3 16
J2
IO L2N T0 AD12N 35
V10
PROGRAM B 0
U11
INIT B0
U12
DONE 0
D19
IO LIN T0 D01 DIN 14
C11
CCLK 0
T1
IO L3P T0 DQS 34
T2
IO LIN T0 34
U1
IO L3N T0 DQS 34
T3
IO L2N T0 34
R2
IO L1P T0 34
N17
IO L13P T2 MRCC 14
W17
IO L20N T3 Ao7 D23 14
U19
IO L15P T2 DQS RDWR B 14
W13
IO L22P T3 A05 D21 14
U16
IO L23N T3 A02 D18 14
EVF LVDSD0P
L18
IO L8P T1 D11 14
EVF LVDSD0N
IO L8N T1 D12 14
K18
EVF LVDSD1P
G18
IO L2P T0 D02 14
EVF LVDSD1N
W16
IO L20P T3 A08 D24 14
F18
IO L2N T0 D03 14
EVF LVDSD2P
IO L5P T0 D06 14
H17
W5
IO L12P T1 MRCC 34
EVF LVDSD2N
IO L5N T0 D07 14
G17
W2
IO L5N T0 34
EVF LVDSCKP
IO L12P T1 MRCC 14
L17
EVF LVDSCKN
V5
IO L16N T2 34
K17
IO L12N T1 MRCC 14
IO L19N T3 VREF 34
V7
U8
IO L14P T2 SRCC 34
D0 P
D0 N
D1 P
D1 N
CLKP
FL6005
3
2
CLKN
4
1
PW LCD1.8V
FL6007
3
2
4
1
RST
FL6006
3
2
4
1
EVF SDI
EVF SCK
EVF SDO
EVF CS
RESET
D0 P
D0 N
D1 P
D1 N
D2 P
D2 N
CLK P
CLK N
IC901
(SUB LVDS)
D0+
B1
R0
F6
D0-
A1
R7
H5
D1+
F1
G0
A7
D1-
E1
G7
E7
N x PCLK
CLK+
D1
B0
A3
PLL
0
B7
B6
CLK-
C1
1
DDR
SDR
FSS
HS
F/XS
H4
F2
VS
LS0
G3
D4
PCLK
PSEL0
D3
G4
FM
CONFIGURATION
D5
FSS
AND
E5
POWER MANAGEMENT
LS0
D4
PSEL1
E3
TX/RX
C2
XSD
G2
S DO LCD
S CS LCD
S CLK LCD
IC903
(LCD POWER CONTROL)
6
VIN
PW REG3V
CTRL A
CTRL B
EVF
UNIT
HC-X1 VIDEO/AUDIO PROCESS CIRCUIT ( 2 ) BLOCK DIAGRAM
IC902
(LCD DRIVER)
B8
DI0
DO0
E8
BRGOUT R0-7
C6
DI7
DO7
G7
A5
DI8
DO8
H9
BRGOUT G0-7
B3
DI15
DO15
J6
C3
DI16
DO16
G5
BRGOUT B0-7
DI23
DO23
D3
H3
XHDIN
C9
B9
XVDIN
LCD
A8 CLKIN
PANEL
XHD OUT
E9
XVD OUT
D9
D8
CLK OUT
D7
DE OUT
F1
SI
F2
XCS
G2 XSCK
XRSTIN
J3
CH907
CH906
CH905
VSP
1
VSN
2
4
5
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