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8.2
Diagram
SSB: Front End
Block Diagram
Pin Configuration
VSSAH_OSC
VDDAH_OSC
I2C_SDA2
I2C_SCL2
B02B, DRX3926K (IC 7T50)
RF AGC
IF AGC
SAW
Main
IF AMP
Tuner
Integrated Tuner
2
I
C
VSSAH_CVBS
VDDAH_CVBS
CVBS
SIF
VSSAL_AFE2
VDDAL_AFE2
PDP
PDN
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
XI
49
XO
50
51
52
VDDH
53
VSSH
54
VSSL
55
VDDL
56
DRXK
TDO
57
TMS
58
TCK
59
TDI
60
61
62
I2S_CL
63
I2S_DA
64
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
I2S_WS
VDDL
VSSL
GPIO1
MSTRT
MERR
VSSH
VDDH
Figure 8-2 Pin configuration
IC Data Sheets
ADC
DVB-T/QAM/ATV
Stereo Decoder
Presaw
Sense
INP
INN
VSSAH_AFE1
VDDAH_AFE1
VDDAL_AFE1
VSSAL_AFE1
IF_AGC
RF_AGC
32
RSTN
31
SAW_SW
30
GPIO2
29
VSYNC
28
VSSL
27
VDDL
26
VDDH
25
VSSH
24
I2C_SDA1
23
I2C_SCL1
22
MD7
21
MD6
20
MD5
19
MD4
18
VDDH
17
VSSH
VDDL
VSSL
MD3
MD2
MD1
MD0
MVAL
MCLK
Q549.5E LA
DVB-T/QAM
FEC
DAC
Demodulator
DAC
System Controller
18440_300_090303.eps
8.
EN 47
MPEG-2
TS
CVBS
SIF
2
I
S Audio
2
I
C
GPIO
090303
2009-Sep-11
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