Table of Contents
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Circuit Diagrams and PWB Layouts
SSB: FPGA WOW - I/O Banks
1
2
3
4
A
2F43 E7
2FN2 D9
2FN6 D13
3F74-3 B2
3FN2 B1
2FN0 D9
2FN3 D9
2FN7 D13
3F74-4 B5
3FN3 B1
2FN1 D9
2FN5 D12
3F74-2 B4
3FN1 A1
3FNF E7
1
2
3
B
FPGA WOW - IO-BANKS
+1V2-PLL
C
7FN0-1
EP3C40F324C7N
A
VCCD_PLL3
BANK1
F2
CLK0|CLK_0P
IFN0
F1
CLK1|CLK_0N
FF18
3FN1 1K0
nCE
nCE
K6
CE
D
3FN2
nCONFIG
H5
nCONFIG
3F74-3
CONFIG
47R
DCLK
3
6
H4
+3V3-FPGA
FF48
10K
nSTATUS
DCLK
nSTATUS
G5
STATUS
TCK
J1
3FN3 10K
+3V3-FPGA
TCK
IO_E2|L10P|FLASH_CE_|CSO_
FF19
TDI
J6
TDI
TDO
J5
TDO
B
TMS
J2
TMS
C2
IO_C2|VREFB1N0
F3
E
IO_F3|VREFB1N1
H6
IO_H6|VREFB1N2
H1
IO_H1|VREFB1N3
F
C
+1V2-PLL
+2V5-PLL
7FN0-5
EP3C40F324C7N
VCCD_PLL4
VCCA4
BANK5
G
TX851CLK+
N17
L16
IFNH
CLK6|CLK_3P
IO_L16|R33P
M17
IFNJ
IO_M17|R33N
TX851CLK-
N18
L14
TX851A+
CLK7|CLK_3N
IO_L14|R36P
D
L15
TX851A-
IO_L15|R36N
TX851B+
L18
L13
TX851D+
IO_L18|VREFB5N0
IO_L13|R38P
N16
M14
TX851D-
IO_N16|VREFB5N1
IO_M14|R38N
R17
P17
TX851E+
IO_R17|VREFB5N2
IO_P17|R42P
R18
P18
MSEL0
TX851E-
IO_R18|VREFB5N3
IO_P18|R42N
T17
MSEL1
IO_T17|R54N
H
TX851B+
K17
N15
MSEL2
IO_K17|R29P
IO_N15|R55P
K18
T18
TX851B-
MSEL3
IO_K18|R29N
IO_T18
TX851C+
L17
T16
IO_L17|R32P|DEV_CLR_
IO_T16|RUP3
TX851C-
M18
R16
IO_M18|R32N|DEV_OE
IO_R16|RDN3
GNDA4
E
I
J
+1V2-FPGA
F
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
K
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
G
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
L
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-FPGA
M
H
N
1
2
3
O
P
1
2
3
4
Q549.5E LA
10.
5
6
7
8
9
3FNG E7
7FN0-2 A6
7FN0-5 C1
7FN0-8 C13
9FN1 D4
9FN7 E4
7FN0-1 A3
7FN0-3 A10
7FN0-6 C5
7FN0-9 E4
9FN4 E4
9FN8 D5
7FN0-10 F11
7FN0-4 A13
7FN0-7 C10
9FN0 D4
9FN6 E4
9FN9 D7
4
5
6
+2V5-PLL
+1V2-PLL
+2V5-PLL
7FN0-2
VCCA3
EP3C40F324C7N
VCCD_PLL1
VCCA1
BANK2
IFN1
B2
N2
IO_B2|L1P
CLK2|CLK_1P
B1
IO_B1|L1N
C1
N1
IO_C1|L3N
CLK3|CLK_1N
C3
IO_C3|L4P|RESET_
D3
L6
IO_D3|L7P
IO_L6|VREFB2N0
D2
M3
IO_D2|L8P
3F74-2
IO_M3|VREFB2N1
D1
4
5
ASDO
R1
IO_D1|L8N|DATA1|ASDO
IO_R1|VREFB2N2
E2
47R
3F74-4
nCSO
R5
IO_R5|VREFB2N3
7
E1
2
IO_E1|L10N
47R
G2
TXF1A+
K2
IO_G2|L20P
IO_K2|L26P
G1
TXF1A-
K1
IO_G1|L20N
IO_K1|L26N
H2
K5
IO_H2
IO_K5|L28P
H3
DATA0
L5
IO_H3|DATA0
IO_L5|L28N
TXF1B+
L2
IO_L2|L32P
GNDA1
GNDA3
+1V2-PLL
+2V5-PLL
7FN0-6
EP3C40F324C7N
VCCD_PLL2
VCCA2
BANK6
+3V3-FPGA
IFNG
F17
B18
CLK4|CLK_2P
IO_B18|R4N|PADD20
CLK-OUT2-PNX5100
C17
IO_C17|R5P|PADD21
CLK-OUT-PNX5100
9FN8
F18
C18
CLK5|CLK_2N
IO_C18|R5N|PADD22
G14
IO_G14|R7N|PADD23
CONF-DONE
K14
H13
CONF_DONE
IO_H13|R8P|RDY
H14
IO_H14|R8N|AVD_
IFNK
K13
D17
MSEL0
IO_D17|R12P|OE_
IFNL
J18
D18
MSEL1
IO_D18|R12N|WE_
IFNM
J17
IO_H16|R23N H16
MSEL2
IFNN
J14
IO_E17|R24P|CLKUSR E17
MSEL3
IO_E18|R24N|CEO_ E18
B17
BACKLIGHT-OUT2
IO_G17|R27P|CRC_ERROR G17
IO_B17|VREFB6N0
CON23
H15
IO_G18|R27N|INIT_DONE G18
IO_H15|VREFB6N1
H18
CON20
IO_H17|R28P H17
IO_H18|VREFB6N2
J13
IO_J13|VREFB6N3
GNDA2
7FN0-9
EP3C40F324C7N
VCC
F4
+3V3-FPGA
F10
G4
VCCIO1
+3V3-FPGA
F12
J4
+3V3-FPGA
F6
F8
K4
+2V5out-FPGA
G10
M4
VCCINT
VCCIO2
+2V5out-FPGA
G11
N4
+2V5out-FPGA
G12
G13
R6
+2V5out-FPGA
G7
R7
VCCIO3
+2V5out-FPGA
G8
R9
VCCINT
+2V5out-FPGA
H12
H7
R10
+2V5in-FPGA
J12
R12
VCCIO4
+2V5in-FPGA
J7
R14
+2V5in-FPGA
K12
VCCINT
K7
K15
+2V5in-FPGA
L12
M15
+2V5in-FPGA
VCCIO5
L7
R15
+2V5in-FPGA
M11
M12
F16
VCCINT
+3V3-FPGA
M6
G15
VCCIO6
+3V3-FPGA
M7
J15
+3V3-FPGA
M8
M9
D11
+2V5-DDR1
N11
D13
VCCINT
VCCIO7
+2V5-DDR1
N13
D15
+2V5-DDR1
N7
N9
D4
+2V5-DDR1
D6
VCCIO8
+2V5-DDR1
D8
+2V5-DDR1
4
5
6
5
6
7
8
9
EN 101
10
11
12
13
9FNA D7
9FND C9
FF48 B1
IFN2 B8
IFN5 B9
IFN8 B13
9FNB D7
FF18 A1
IFN0 A2
IFN3 B8
IFN6 B11
IFN9 B13
9FNC E7
FF19 B1
IFN1 A4
IFN4 B9
IFN7 B11
IFNA B15
7
8
9
10
7FN0-3
EP3C40F324C7N
BANK3
L1
TXF1B-
U9
IO_L1|L32N
CLK15|CLK_6P
IO_U5|B18P
L4
TXF1C+
IO_L4|L33P
IO_V5|B18N
L3
V9
TXF1C-
IO_L3|L33N
CLK14|CLK_6N
IO_R8|B21P
M2
TXF1CLK+
IO_M2|L34P
IO_T8|B21N
M1
P8
TXF1CLK-
IO_M1|L34N
IO_P8|VREFB3N0
IO_P9|B23N
P2
TXF1D+
P7
IO_P2|L44P
IO_P7|VREFB3N1
IO_U6|B24P
P1
TXF1D-
T6
IO_P1|L44N
IO_T6|VREFB3N2
IO_V6|B24N
R2
T4
IO_R2|L45P
IO_T4|VREFB3N3
IO_U7|B26P
T3
TXF1E+
IO_T3|L52P
IO_V7|B26N
R3
U1
TXF1E-
IO_R3|L52N
IFN4
IO_U1|B1P
IO_U8|B27P
M5
V1
IO_M5
IFN5
IO_V1|B1N
IO_V8|B27N
R4
P6
IO_R4
IO_P6|B6P
IO_U2|PLL1_CLKOUTP
T2
TXF2A+
U3
IFN2
IO_T2|RUP1
IO_U3|B16P
IO_V2|PLL1_CLKOUTN
T1
TXF2A-
V3
IO_T1|RDN1
IFN3
IO_V3|B16N
TXF2B+
U4
IO_U4|B17P
TXF2B-
V4
IO_V4|B17N
9FND
CLK-OUT2-PNX5100
7FN0-7
RES
EP3C40F324C7N
BANK7
IFNF
B10
CLK9|CLK_5P
IO_B14|T36P|PADD6
CON27
IO_A14|T36N|PADD5
9FN9
SCL-AMBI-3V3
A10
CLK8|CLK_5N
IO_B15|T37P|PADD4
RES
IO_A15|T38N|PADD3
A17
VREF-FPGA1
IO_A17|VREFB7N0
IO_B16|T41P|PADD2
D12
VREF-FPGA1
IO_D12|VREFB7N1
IO_A16|T41N|PADD1
C12
CON26
VREF-FPGA1
IO_C12|VREFB7N2
IO_E12|T45P|PADD0
9FNA
RES
SDA-AMBI-3V3
E11
VREF-FPGA1
IO_E11|VREFB7N3
CON22
9FNB
RES
BACKLIGHT-OUT
D10
MM1-A2
IO_D10|T27P|PADD14
RES
BACKLIGHT-CONTROL-FPGA-IN
MM1-A3
C10
IO_C10|T27N|PADD13
9FNC
MM1-A0
B11
3FNF
SDA-SSB
IO_B11|T29P|PADD12
3FNG
100R
SCL-SSB
MM1-A1
A11
IO_A11|T29N|PADD11
IO_D14|PLL2_CLKOUTP
100R
CON21
MM1-A10
B12
IO_B12|T31P|PADD10
IO_C14|PLL2_CLKOUTN
MM1-D1
A12
IO_A12|T31N|PADD9
MM1-D2
B13
IO_B13|T35P|PADD8
MM1-CS0
A13
IO_A13|T35N|PADD7
7
8
9
10
10
11
12
13
2009-Sep-11
14
15
16
17
18
IFNB B15
IFNF D7
IFNJ D3
IFNM D5
IFNC D13
IFNG D5
IFNK D4
IFNN D5
IFND E11
IFNH D3
IFNL D4
11
12
13
14
7FN0-4
EP3C40F324C7N
BANK4
U5
TXF2C+
V5
TXF2C-
TX852CLK+
U10
CLK13|CLK_7P
IO_U14|B34P
R8
IO_V14|B34N
T8
TX852CLK-
V10
CLK12|CLK_7N
IO_U15|B35P
P9
P13
IO_P13|VREFB4N0
IO_V15|B35N
U6
TXF2CLK+
U16
IO_U16|VREFB4N1
IO_R11|B36N
V6
TXF2CLK-
T11
IO_T11|VREFB4N2
IO_V16|B44N
U7
TXF2D+
V12
IO_V12|VREFB4N3
IO_U17|B47P
V7
TXF2D-
IO_V17|B47N
U8
TXF2E+
U11
TX852E+
IO_U11|B28P
IO_R13|B48N
V8
TXF2E-
TX852E-
V11
IO_V11|B28N
U2
U12
IFN6
IO_U12|B29P
IO_T13|RUP2
V2
TX852D+
U13
IFN7
IO_U13|B32P
IO_T14|RDN2
TX852D-
V13
IO_V13|B32N
IO_U18|PLL4_CLKOUTP
P10
IFN8
IO_P10|B33P
IO_V18|PLL4_CLKOUTN
P11
IFN9
IO_P11|B33N
7FN0-8
EP3C40F324C7N
BANK8
IFNC
B14
MM1-D4
B9
CLK11|CLK_4P
IO_C5|T11P|DATA5
A14
MM1-D3
IO_B5|T16P|DATA13
B15
MM1-RAS
A9
CLK10|CLK_4N
IO_A5|T16N|DATA14
A15
MM1-D5
IO_B6|T18P|DATA15
B16
E9
MM1-D6
VREF-FPGA1
IO_E9|VREFB8N0
IO_A6|T18N|PADD19
A16
MM1-CAS
C7
VREF-FPGA1
IO_C7|VREFB8N1
IO_B7|T19P|DATA4
E12
D7
MM1-D0
VREF-FPGA1
IO_D7|VREFB8N2
IO_A7|T19N|PADD18
A18
MM1-D7
E6
VREF-FPGA1
IO_A18|T48P
IO_E6|VREFB8N3
IO_B8|T20P|DATA3
D16
IO_D16|T49P
IO_A8|T20N|DATA2
C16
MM1-WE
D5
MM1-A8
IO_C16|T49N
IO_D5|T3P|DATA12
IO_D9|T24P|PADD17
E14
MM1-BA0
MM1-A12
B3
IO_E14|RUP4
IO_B3|T4P|DATA11
IO_C9|T24N|PADD16
E13
MM1-CKE
A3
MM1-BA1
IO_E13|RDN4
IO_A3|T4N|DATA10
IO_E10|T25P|PADD15
D14
MM1-A6
E7
IFND
IO_E7|T5N|DATA9
IO_A2|PLL3_CLKOUTP
C14
MM1-A11
B4
IO_B4|T6P|DATA8
IO_A1|PLL3_CLKOUTN
MM1-D8
A4
IO_A4|T7N|DATA7
MM1-D15
E8
IO_E8|T8P|DATA6
7FN0-10
EP3C40F324C7N
GND
C4
K3
C6
K8
C8
K9
C11
K10
C13
K11
C15
K16
GND
GND
E3
L8
E16
L9
F7
L10
F9
L11
F11
M10
GND
GND
F13
M13
G3
M16
G6
N3
G9
N6
G16
N8
GND
GND
H8
N10
H9
N12
H10
P3
H11
P16
J3
T5
GND
GND
J8
T7
J9
T9
J10
T10
J11
T12
J16
T15
11
12
13
14
C
H
N
S
E
T
N
A
M
E
CLASS_NO
FPGA WOW - IO-BANKS
TV543 R2 LDIPNX
2008-10-10
3
NAME
Maelegheer Ingrid
SUPERS.
8
CHECK
DATE
2007-12-06
ROYAL PHILIPS ELECTRONICS N.V. 2007
C
14
15
16
17
18
19
20
A
15
B
C
A
U14
TX852C+
V14
TX852C-
U15
TX852B+
V15
D
TX852B-
R11
V16
U17
TX852A+
V17
TX852A-
R13
P12
B
IO_P12
T13
T14
U18
IFNA
E
V18
IFNB
C
F
G
C5
MM1-D9
B5
MM1-A9
A5
MM1-DQS1
D
B6
MM1-A7
A6
MM1-D10
B7
MM1-D11
A7
MM1-D12
B8
MM1-A5
H
A8
MM1-D13
D9
MM1-DQS0
C9
MM1-D14
E10
MM1-A4
A2
MM1-CLK+
A1
MM1-CLK-
E
I
J
F
K
G
L
M
H
N
15
O
2
2008-11-21
8204 000 8933
P
130
7
A2
19
20
18310_533_090303.eps
090902
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