MaxLinear XR17V35 Series Design Manual

Pcie uarts
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TBD/18
XR17V35x
PCIe UARTs
Design Guide
MaxLinear Confidential
MaxLinear Confidential
• www.maxlinear.com •
200DGR00
200DGR00
i

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Summary of Contents for MaxLinear XR17V35 Series

  • Page 1 XR17V35x PCIe UARTs Design Guide MaxLinear Confidential MaxLinear Confidential • www.maxlinear.com • 200DGR00 TBD/18 200DGR00...
  • Page 2 XR17V35x PCIe UARTs Design Guide Revision History Revision History Document No. Release Date Change Description 200DGR00 4/24/20 Initial release. 4/24/20 200DGR00...
  • Page 3 XR17V35x PCIe UARTs Design Guide Table of Contents Table of Contents Introduction................................. 1 Reference Documentation ..........................1 Pin Groups ................................1 Design and Layout Recommendations ......................2 4/24/20 200DGR00...
  • Page 4 XR17V35x PCIe UARTs Design Guide List of Tables List of Tables Table 1: PCIe Interface............................2 Table 2: Buck Regulator Output ........................... 2 Table 3: XR17V354 / XR17V358 PCIe UART Expansion Interface Signals............2 Table 4: Other PCIe UART "Special Handling" Device Pins ................3 Table 5: Analog Voltage Inputs..........................
  • Page 5 Reference Documentation XR17V352 Data Sheet XR17V354 Data Sheet XR17V358 Data Sheet Visit www.maxlinear.com to obtain copies of these documents. Pin Groups The tables below are arranged by the following pin groups: ■ PCIe Interface ■ Buck Regulator Output ■...
  • Page 6 XR17V35x PCIe UARTs Design Guide Design and Layout Recommendations Design and Layout Recommendations Table 1: PCIe Interface Schematic Design Recommendations TX +/- and RX +/- must be AC coupled using 100nF 0603 or smaller (0402) recommended) ceramic capacitors at the transmitting source.
  • Page 7 XR17V35x PCIe UARTs Design Guide Design and Layout Recommendations Table 4: Other PCIe UART "Special Handling" Device Pins Schematic Design Recommendations Device Reset Internally logically “AND”ed together. Connect PERST# to PCIe edge connector reset input. Connect RESET# to PERST# or connect to pull-up. CLKREQ# CLKREQ# support is optional in PCIe specification and is not supported in the XR17V35x device.
  • Page 8 Products are not authorized for use in such applications unless MaxLinear, Inc. receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of MaxLinear, Inc.

This manual is also suitable for:

Xr17v352Xr17v354Xr17v358

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