MaxLinear XR17V358 Manual

High performance octal pci express uart

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JULY 2018

GENERAL DESCRIPTION

The

XR17V358

is a single chip 8-channel PCI

Express (PCIe) UART (Universal Asynchronous

Receiver and Transmitter), optimized for higher

performance and lower power.

serves as a single lane PCIe bridge to 8 independent

enhanced 16550 compatible UARTs. The XR17V358

is compliant to PCIe 2.0 Gen 1 (2.5 GT/s).

In addition to the UART channels, the XR17V358 has

16 multi-purpose I/Os (MPIOs), a 16-bit general

purpose counter/timer and a global interrupt status

Each UART of the XR17V358 has many enhanced

features such as the 256-bytes TX and RX FIFOs,

programmable Fractional Baud Rate Generator,

Automatic Hardware or Software Flow Control, Auto

RS-485 Half-Duplex Direction Control, programmable

TX and RX FIFO Trigger Levels, TX and RX FIFO

Level Counters, infrared mode, and data rates up to

31.25 Mbps. The XR17V358 is available in a 176-pin

FPBGA package (13 x 13 mm).

Covered by U.S. Patents #5,649,122, #6,754,839,

OTE

#6,865,626 and #6,947,999

APPLICATIONS



Next generation Point-of-Sale Systems



Remote Access Servers



Storage Network Management



Factory Automation and Process Control



Multi-port RS-232/RS-422/RS-485 Cards

1. B

IGURE

LOCK

IAGRAM OF THE

T X +

T X -

R X +

R X -

C L K +

C L K -

C L K R E Q #

P E R S T #

E N 4 8 5 #

E N IR #

E E C K

E E D I

E E D O

E E C S

D [7 : 0 ]

S E L

C L K

IN T

M O D E

P R E S

HIGH PERFORMANCE OCTAL PCI EXPRESS UART

FEATURES



The XR17V358



XR17V358

C o n f ig u r a t io n

S p a c e

B u c k R e g u la to r

R e g is t e r s

1 2 5 M H z C lo c k

P C Ie

P C I L o c a l

In t e r f a c e

B u s

In te r fa c e

G lo b a l

C o n fig u r a tio n

C o n f ig u r a t io n

R e g is te r s

S p a c e

E E P R O M

R e g is t e r s

In te r fa c e

E x p a n s io n

1 6 - b it

T im e r /C o u n te r

In te r f a c e

Single 3.3V power supply

Internal buck regulator for 1.2V core

PCIe 2.0 Gen 1 compliant

x1 Link, dual simplex, 2.5 Gbps in each direction

Expansion bus interface

EEPROM interface for configuration

Global interrupt status register for all eight UARTs

Up to 31.25 Mbps serial data rate

16 multi-purpose inputs/outputs (MPIOs)

16-bit general purpose timer/counter

Sleep mode with wake-up Indicator

Eight independent UART channels controlled with

16550 compatible register Set

■

256-byte TX and RX FIFOs

■

Programmable TX and RX Trigger Levels

■

TX/RX FIFO Level Counters

■

Fractional baud rate generator

■

Automatic RTS/CTS or DTR/DSR hardware

■

flow control with programmable hysteresis

Automatic Xon/Xoff software flow control

■

RS-485 half duplex direction control output

■

with programmable turn-around delay

Multi-drop with Auto Address Detection

■

Infrared (IrDA 1.1) data encoder/decoder

■

Software compatible to XR17C15x, XR17D15x,

XR17V25x PCI UARTs

U A R T C h a n n e l 0

T X [ 7 : 0 ]

2 5 6 - b y t e T X F IF O

6 4 - b y t e T X F IF O

U A R T

R X [ 7 : 0 ]

R X [ 7 :0 ]

R e g s

T X & R X

E N D E C

2 5 6 - b y t e R X F IF O

B R G

6 4 -

6 4 - b y t e R X F IF O

R T S # [7 : 0 ]

U A R T C h a n n e l 1

D T R # [ 7 :0 ]

D T R # [7 : 0 ]

U A R T C h a n n e l 2

C T S # [7 :0 ]

U A R T C h a n n e l 3

D S R # [7 :0 ]

U A R T C h a n n e l 4

U A R T C h a n n e l 5

D C D # [ 7 : 0 ]

U A R T C h a n n e l 6

R I# [ 7 : 0 ]

U A R T C h a n n e l 7

M P IO [ 1 5 : 0 ]

M P IO [7 :0 ]

M u lti- p u r p o s e

In p u ts /O u t p u t s

C r y s ta l O s c /B u ff e r

T M R C K

XR17V358

REV. 1.0.6

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Summary of Contents for MaxLinear XR17V358

Page 1 Expansion bus interface is compliant to PCIe 2.0 Gen 1 (2.5 GT/s).  EEPROM interface for configuration In addition to the UART channels, the XR17V358 has  16 multi-purpose I/Os (MPIOs), a 16-bit general Global interrupt status register for all eight UARTs purpose counter/timer and a global interrupt status ...
Page 2 ETHOD XR17V358IB176-F -40°C to +85°C 176-FPBGA Tray XR17V358/SP339-0A-EB XR17V358 8-Channel Evaluation Board XR17V358/SP339-E4-EB XR17V358 12-Channel Evaluation Board (Master / Slave) XR17V358/SP339-E8-EB XR17V358 16-Channel Evaluation Board (Master / Slave) OTES 1. Refer to www.exar.com/XR17V358 for most up-to-date Ordering Information. 2. Visit www.exar.com...
Page 3 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 PIN DESCRIPTIONS ESCRIPTION PCIe SIGNALS CLK+ PCIe reference clock input. (Nominal single-ended swing from 0 to 700 mV.) CLK- PCIe differential TX outputs. Must be AC coupled using 0.1 uF non-polarized capacitor (0603 or smaller) near the transmitting source.
Page 4 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 PIN DESCRIPTIONS ESCRIPTION DSR1# UART channel 1 Data Set Ready or general purpose input (active LOW). If unused, a pull-up or pull-down resistor is recommended on this pin. CD1# UART channel 1 Carrier Detect or general purpose input (active LOW). If unused, a pull-up or pull-down resistor is recommended on this pin.
Page 5 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 PIN DESCRIPTIONS ESCRIPTION UART channel 4 Receive Data or infrared receive data. Normal RXD input idles at HIGH condition. The infrared pulses can be inverted prior to decoding by setting FCTR bit [4]. If unused, a pull-up or pull-down resistor is ...
Page 6 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 PIN DESCRIPTIONS ESCRIPTION DSR6# UART channel 6 Data Set Ready or general purpose input (active LOW). If unused, a pull-up or pull-down resistor is recommended on this pin. CD6# UART channel 6 Carrier Detect or general purpose input (active LOW). If unused, a pull-up or pull-down resistor is recommended on this pin.
Page 7 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 PIN DESCRIPTIONS ESCRIPTION Expansion Interface Data 3 with internal pull-down resistor. If a slave device is present, connect between master and slave with trace capacitance of less than 25 pF. Leave unconnected if no slave device is present.
Page 8 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 PIN DESCRIPTIONS ESCRIPTION Multi-purpose input/output 5. This pin defaults to an input with interrupts  MPIO5 disabled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T, MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull- down resistor is recommended on this pin.
Page 9 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 PIN DESCRIPTIONS ESCRIPTION EEPROM SIGNALS EECK Serial clock output uses the internal 125 MHz clock divided by 256 (488 KHz) following power-up or reset to read an external EEPROM. This pin may also be manually clocked using the Configuration Register REGB.
Page 10 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 PIN DESCRIPTIONS ESCRIPTION TEST0 Factory Test Modes. For normal operation, connect to GND. TEST1 TEST2 POWER / GROUND / NO CONNECT VCC33 D5, D9, E12, 3.3V I/O power supply. J12, M7 VCC33A 3.3V analog PHY power supply.
Page 11 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 FUNCTIONAL DESCRIPTION The XR17V358 integrates the functions of eight independent enhanced 16550 UARTs, a general purpose 16- bit timer/counter, and 16 multi-purpose I/Os (MPIOs). Each UART channel has its own 16550 UART compatible configuration register set for individual channel control, status and data transfer.
Page 12 XR17V358 software compatible with the previous generation PCI UARTs. Minimal changes are needed to the software driver of an existing Exar PCI UART driver so that it can be used with the XR17V358 PCIe UART. There are three different sets of registers as shown in Figure 4.
Page 13 HEX OR BINARY 0x00 31:16 Device ID - No slave device on expansion interface 0x0358 Device ID - XR17V358 slave device on expansion interface 0x8358 Device ID - XR17V354 slave device on expansion interface 0x4358 15:0 Vendor ID (Exar) specified by PCISIG...
Page 14 31:14 Memory Base Address Register (BAR0) 0x00000 13:0 These 14 bits are hardwired to 0 in the XR17V358 to inform the 0x0000 PCIe host to allocate 16k of memory space for accessing the Device Configuration and UART Configuration Registers. 0x14...
Page 15 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 1: PCI L ABLE OCAL ONFIGURATION PACE EGISTERS DDRESS ESET ALUE ESCRIPTION FFSET HEX OR BINARY 0x78 31:16 PME# support (PME# can be asserted from D3hot and D0) 0x4803 PCI Power Management 1.2...
Page 16 : EWR=Read/Write from external EEPROM. RWR=Read/Write. RO= Read Only. RWC=Read/Write-Clear. EEPROM Interface The XR17V358 provides an interface to an Electrically Erasable Programmable Read Only Memory (EEPROM). The EEPROM must be a 93C46-like device, with its memory configured as 16-bit words. This interface is provided in order to program the registers in the PCI Configuration Space of the PCI UART during power-up.
Page 17 The Device Configuration Registers and the eight individual UART Configuration Registers of the XR17V358 occupy 8K of PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration register set.
Page 18 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 4: XR17V358 UART ABLE EVICE ONFIGURATION EGISTERS FFSET DDRESS EMORY PACE RITE OMMENT 0x0000 - 0x000F UART channel 0 Regs Table 13 First 8 regs are 16550 compatible & Table 14...
Page 19 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 4: XR17V358 UART ABLE EVICE ONFIGURATION EGISTERS FFSET DDRESS EMORY PACE RITE OMMENT Table 13 0x1000 - 0x100F UART channel 4 Regs First 8 regs are 16550 compatible & Table 14...
Page 20 The Device Configuration Registers provide easy programming of general operating parameters to the XR17V358 and for monitoring the status of various functions. These registers control or report on all 8 channel UARTs functions that include interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft-reset control, and device identification and revision, and others.
Page 21 INT0 [7:0] All bits start up zero. A special interrupt condition is generated by the XR17V358 upon awakening from sleep after all eight channels were put to sleep mode earlier. This wake-up interrupt is cleared by a read to the INT0 register.
Page 22 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 INT0 [7:0] Channel Interrupt Indicator Each bit gives an indication of the channel that has requested for service. Bit [0] represents channel 0 and bit [7] indicates channel 7. Logic 1 indicates the channel N [7:0] has called for service. The interrupt bit clears after reading the appropriate register of the interrupting channel register, see Interrupt Clearing section.
Page 23 DEFAULT XX-XX-00-00) The XR17V358 has a general purpose 16-bit timer/counter. The internal 125 MHz clock (master mode) or 62.5 MHz clock (slave mode) or the external clock at the TMRCK input pin can be selected as the clock source for the timer/counter.
Page 24 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 16-Bit Timer/Counter Programmable Registers TIMERMSB Register TIMERLSB Register Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10 Bit-9 Bit-8 REGA [15:8] Register Reserved. TIMERCNTL [7:0] Register The bits [3:0] of this register are used to issue commands.
Page 25 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 TIMER OPERATION The following paragraphs describe the operation of the 16-bit Timer/Counter. The following conventions will be used in this discussion: ’N’ is the 16-bit value programmed in the TIMER MSB, LSB registers ■...
Page 26 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 7. T IGURE IMER UTPUT IN HOT AND TRIGGERABLE ODES START TIMER COMMANDS ISSUED: LESS THAN 'N' START TIMER CLOCKS BETWEEN SUCCESSIVE COMMANDS STOP TIMER START TIMER COMMAND ISSUED COMMAND ISSUED...
Page 27 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 8X sampling rate. Transmit and receive data rates will double by selecting 8X. If using the 4XMODE, the corresponding bit in this register should be logic 0 8XMODE Register Individual UART Channel 8X Clock Mode Enable...
Page 28 8-bit content in the DVID register provides device identification. A return value of 0x88 from this register indicates the device is a XR17V358. The DREV register returns an 8-bit value of 0x01 for revision A with 0x02 equals to revision B and so on. This information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes.
Page 29 1.4.8 Multi-Purpose Inputs and Outputs The XR17V358 provides 16 multi-purpose inputs/outputs MPIO[15:0] for general use. Each pin can be programmed to be an input or output function. The input logic state can be set for normal or inverted level, and optionally set to generate an interrupt.
Page 30 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 1.4.9 MPIO REGISTERS There are 2 sets of 6 registers that select, control and monitor the 16 multipurpose inputs and outputs. Figure 9 shows the internal circuitry 9. M IGURE ULTIPURPOSE...
Page 31 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 MPIOLVL Register Multipurpose Output Level Control Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIO3T [15:0] (default 0x00) The MPIO outputs can be tri-stated by the MPIO3T register. A logic 0 (default) sets the output to active level per register MPIOBIT settling, a logic 1 sets the output pin to tri-state.
Page 32 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 MPIOOD [15:0] (default 0x00) The MPIO outputs can behave as an open-drain output by the MPIOOD register. When the MPIOOD register is a logic 0 (default), the MPIO is not an open-drain output. A logic 1 enables the MPIO as an open-drain output.
Page 33 This is a 16-bit or 32-bit read operation where the Line Status Register (LSR) content in the UART channel register is paired along with the data byte. This operation further facilitates data unloading with the error flags without having to read the LSR register separately. Furthermore, the XR17V358 supports 32-bit read/write operation.
Page 34 Special Rx FIFO Data Unloading at locations 0x0200, 0x0600, 0x0A00, 0x0E00, 0x1200, 0x1600, 0x1A00, and 0x1E00 The XR17V358 also provides the same RX FIFO data along with the LSR status information of each byte side- by-side, at locations 0x0200 (channel 0), 0x0200 (channel 1), 0x0A00 (channel 2), .., 0x1E00 (channel 7).
Page 35 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 Channel 0 to 7 Transmit Data in 32-bit alignment through the Configuration Register Address 0x0100, 0x0500, 0x0900, 0x0D00, 0x1100, 0x1500, 0x1900 and 0x1D00 Transmit Data Byte n+3 Transmit Data Byte n+2...
Page 36 3.0 UART There are 8 UARTs channel [7:0] in the XR17V358. Each has its own 256-byte of transmit and receive FIFO, a set of 16550 compatible control and status registers, and a baud rate generator for individual channel data rate setting.
Page 37 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 10. B IGURE ENERATOR To Other Channels DLL, DLM and DLD Registers MCR Bit-7=0 Prescaler (default) Divide by 1 125 MHz Clock 16X, 8X or 4X (Master) Sampling Fractional Baud Rate Clock Rate Generator 62.5 MHz Clock...
Page 38 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 11: T 125 MH 16X S ABLE YPICAL DATA RATES WITH NTERNAL Z CLOCK AT AMPLING ASTER EQUIRED IVISOR FOR IVISOR DLM P DLL P DLD P ROGRAM ROGRAM ROGRAM RROR...
Page 39 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 12: T 62.5 MH 16X S ABLE YPICAL DATA RATES WITH Z CLOCK AT AMPLING LAVE EQUIRED IVISOR FOR IVISOR DLM P DLL P DLD P ROGRAM ROGRAM ROGRAM RROR 16x Clock...
Page 40 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation Automatic hardware or RTS/DTR and CTS/DSR flow control is used to prevent data overrun to the local receiver FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request remote unit to suspend/restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart local transmitter.
Page 41 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 11. A RTS/DTR CTS/DSR F IGURE ONTROL PERATION Local UART Remote UART UARTA UARTB Receiver FIFO Transmitter Trigger Reached RTSA# CTSB# Auto RTS Auto CTS Trigger Level Monitor Receiver FIFO Transmitter...
Page 42 REV. 1.0.6 Infrared Mode Each UART in the XR17V358 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.1. The input pin ENIR conveniently activates all 8 UART channels to start up in the infrared mode. This global control pin enables the MCR bit [6] function in every UART channel register. After power up or a reset, the software can overwrite MCR bit [6] if so desired.
Page 43 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit [4] to a logic 1. All regular UART functions operate normally.
Page 44 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 UART CHANNEL CONFIGURATION REGISTERS Address lines A0 to A3 select the 16 registers in each channel. The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8 addresses.
Page 45 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE EFR B HADED BITS ARE ENABLED BY DDRESS OMMENT A3-A0 RITE 0 0 0 0 BIT [7] BIT [6] Bit [5] Bit [4] Bit [3]...
Page 46 Bit [3] Bit-2 Bit [1] Bit [0] MCR bits [3:2] (OP1 and OP2 outputs) are not available in the XR17V358. They are present for 16C550 Figure 13 compatibility during Internal loopback, see Transmitter The transmitter section comprises of a 256 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an 8-bit Transmit Shift Register (TSR).
Page 47 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 14. T -FIFO M IGURE RANSMITTER PERATION IN NON T r a n s m it D a t a H o ld i n g B y t e R e g i s t e r...
Page 48 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The RSR uses the 16X, 8X or 4X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit.
Page 49 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 3.7.2 Receiver Operation with FIFO 17. R FIFO IGURE ECEIVER PERATION IN ONTROL 16X or 8X or 4X Clock Receive Data Shift Data Bit Register (RSR) Validation Receive Data Characters Example: - FIFO trigger level set at 128 bytes - RTS/DTR hyasteresis set at +/-32 chars.
Page 50 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 4.0 UART CONFIGURATION REGISTERS Receive Holding Register (RHR) - Read only SEE”RECEIVER” ON PAGE 48. Transmit Holding Register (THR) - Write only SEE”TRANSMITTER” ON PAGE 46. Baud Rate Generator Divisors (DLM, DLL and DLD) DLM[7:0], DLL[7:0] and DLD[3:0] The Baud Rate Generator (BRG) generates the data rate for the transmitter and receiver.
Page 51 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR bit [0] equals a logic 1 for FIFO enable; resetting IER bits [3:0] enables the XR17V358 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either can be used in the polled mode by selecting respective transmit or receive control bit(s).
Page 52 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 IER[1]: TX Ready Interrupt Enable In non-FIFO mode, a TX interrupt is issued whenever the THR is empty. In the FIFO mode, an interrupt is issued twice: once when the number of bytes in the TX FIFO falls below the programmed trigger level and again when the TX FIFO becomes empty.
Page 53 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6  Wake-up indicator is cleared by a read to the INT0 register. 15: I ABLE NTERRUPT OURCE AND RIORITY EVEL ISR R RIORITY EGISTER TATUS OURCE OF THE INTERRUPT EVEL LSR (Receiver Line Status Register)
Page 54 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 FCR[3]: DMA Mode Select This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy software compatibility.  Logic 0 = Set DMA to mode 0 (default).
Page 55 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 16: T FIFO T ABLE RANSMIT AND ECEIVE RIGGER ABLE AND EVEL ELECTION RANSMIT FCTR FCTR RIGGER ECEIVE RIGGER OMPATIBILITY BIT [7] BIT [6] BIT [7] BIT [6] BIT [5] BIT [4]...
Page 56 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 17: P ABLE ARITY ROGRAMMING BIT [5] BIT [4] BIT [3] ARITY SELECTION No parity Odd parity Even parity Force parity to mark, “1” Forced parity to space, “0” LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit [3] set to a logic 1, LCR bit [4] selects the even or odd parity format.
Page 57 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 Modem Control Register (MCR) - Read/Write The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs. MCR[7]: Clock Prescaler Select (requires EFR bit [4]=1)  Logic 0 = Divide by one. The internal 125 MHz clock (master) or 62.5 MHz clock (slave) is fed directly to the Programmable Baud Rate Generator without further modification, i.e., divide by one (default).
Page 58 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 In Local Loopback mode (MCR[4] = 1), this bit acts as the legacy OP1 output and controls the RI bit in the MSR register, as shown in Figure MCR[1]: RTS# Output The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit [6] and MCR bit [2]=0.
Page 59 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 LSR[2]: Receive Data Parity Error Flag  Logic 0 = No parity error (default).  Logic 1 = Parity error. The receive character in RHR (top of the FIFO) does not have correct parity information and is suspect.
Page 60 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 MSR[2]: Delta RI# Input Flag  Logic 0 = No change on RI# input (default).  Logic 1 = The RI# input has changed from a LOW to a HIGH, ending of the ringing signal. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit [3]).
Page 61 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 18: A RS485 H ABLE DUPLEX IRECTION ONTROL ELAY FROM RANSMIT ECEIVE MSR[7] MSR[6] MSR[5] MSR[4] ELAY IN MSR [3]: Transmitter Disable This bit can be used to disable the transmitter by halting the Transmit Shift Register (TSR). When this bit is set to a logic 1, the bytes already in the FIFO will not be sent out.
Page 62 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 MSR [2]: Receiver Disable This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to a logic 1, the receiver will operate in one of the following ways: If a character is being received at the time of setting this bit, that character will be correctly received.
Page 63 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 FCTR[5]: Auto RS485 Enable Auto RS485 half duplex control enable/disable. RTS# or DTR# can be selected as the control output via MCR bit-2. Note that this feature has precedence over the Auto RTS/DTR flow control feature (EFR bit-6).
Page 64 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 4.14 Enhanced Feature Register (EFR) - Read/Write Enhanced features are enabled or disabled using this register. Bits [3:0] provide single or dual consecutive character software flow control selection (see Table 20). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters.
Page 65 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 EFR[3:0]: Software Flow Control Select Combinations of software flow control can be selected by programming these bits, as shown in Table 20: S ABLE OFTWARE ONTROL UNCTIONS EFR BIT [3] EFR BIT [2]...
Page 66 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 4.18 RXTRG[7:0]: Receive FIFO Trigger Level - Write Only An 8-bit value written to this register, sets the RX FIFO trigger level from 0x01 (one) to 0xFF (255). A value of 0x00 is invalid.
Page 67 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 21: UART RESET CONDITIONS ABLE REGISTERS RESET STATE I/O SIGNALS RESET STATE Bits [7:0] = 0x01 TX[7:0] HIGH Bits [7:0] = 0x00 IRTX[7:0] Bits [7:0] = 0x00 RTS#[7:0] HIGH Bits [7:0] = 0xXX...
Page 68 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 ABSOLUTE MAXIMUM RATINGS Power Supply Range 3.6 Volts Voltage at Any Pin -0.5 to VCC+0.5V Operating Temperature to +85 Storage Temperature to +150 Package Dissipation 500 mW Thermal Resistance (176-FPBGA) θ...
Page 69 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 MECHANICAL DIMENSIONS (176-FPBGA) DETAIL A BOTTOM VIEW TOP VIEW SIDE VIEW DETAIL B TERMINAL DETAILS Drawing No.: POD- 00000136 Revision: A...
Page 70 XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART REV. 1.0.6 RECOMMENDED LAND PATTERN AND STENCIL (176-FPBGA) TYPICAL RECOMMENDED LAND PATTERN TYPICAL RECOMMENDED STENCIL 00000136 Drawing No.: POD- Revision: A...
Page 71 (electronic, mechanical, photocopying, recording, or otherwise), or for any purpose, without the express written permission of MaxLinear, Inc. MaxLinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness.

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