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Maxim Integrated TERIDIAN SEMICONDUCTOR 78M6613 Hardware Design Manuallines

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A Maxim Integrated Products Brand
AN_6613_049
1 Introduction
This application note provides hardware and system design guidelines for those incorporating the
78M6613 System on Chip in their products. These guidelines will help hardware engineers to reduce
design cycle times.
The following topics are discussed:
•
Non-isolated Configuration
Safety Precautions
o
3.3 VDC Supply (V3P3) and System Connections
o
Line Voltage Resistor Divider Selection
o
Shunt Selection and Connections
o
•
Isolated Configuration
Current Transformers
o
Other Connections
o
Voltage Transformers
o
•
Calibration Considerations
•
Basic Configuration
Reset Circuitry
o
In Circuit Emulator (ICE) Pins
o
Connecting 5 V Devices
o
Driving External Loads
o
Connecting I2C EEPROMs
o
Connecting 3-Wire EEPROMs
o
UART0 (TX/RX)
o
Power Supply Topologies
o
•
Timing Reference
Oscillator Connections and Components Selection
o
PCB Layout Recommendations
o
Other Considerations
o
A Hardware Design Checklist is provided at the end of this document as a quick summary.
Rev. 1.0
Hardware Design Guidelines
© 2010 Teridian Semiconductor Corporation
78M6613
APPLICATION NOTE
December 2010
1

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Summary of Contents for Maxim Integrated TERIDIAN SEMICONDUCTOR 78M6613

  • Page 1 78M6613 Hardware Design Guidelines A Maxim Integrated Products Brand APPLICATION NOTE AN_6613_049 December 2010 1 Introduction This application note provides hardware and system design guidelines for those incorporating the 78M6613 System on Chip in their products. These guidelines will help hardware engineers to reduce design cycle times.

  • Page 2: Safety Precautions

    78M6613 Hardware Design Guidelines AN_6613_049 2 Non-isolated Configuration When using a resistive shunt current sensor, the measurement IC and its power domain are not isolated from the AC mains. In this configuration, the 3.3 VDC supply rail (V3P3) for the 78M6613 must be directly connected to AC-Neutral for precision energy measurement.
  • Page 3 AN_6613_049 78M6613 Hardware Design Guidelines 2.2 3.3 VDC Supply (V3P3) and System Connection The 78M6613 requires a single 3.3 VDC supply. The 3.3 VDC (V3P3A pin) also represents the reference potential for the 78M6613. The basic connections for a shunt-based system are represented in Figure 1. LINE 78M 6613 1000 pF...
  • Page 4 78M6613 Hardware Design Guidelines AN_6613_049 Effective 3.3 VDC bypassing incorporates the combination of three different capacitor values. A 1000 pF in parallel with a 0.1 µF ceramic capacitor must be placed as close as possible to the 78M6613 V3P3A pin. Place the 1000 pF capacitor closest to the V3P3A pin of the 78M6613. An additional 22 µF bulk capacitor is placed in the vicinity of the V3P3D pin to provide decoupling for the external DIO circuitry.
  • Page 5 AN_6613_049 78M6613 Hardware Design Guidelines 2.3 Line Voltage Resistor Divider Selection The input line voltage must be scaled to match the 78M6613’s ADC input signal range of ±176.78 mVrms. ���������� ∗ 750 In the example of Figure 3, the line voltage is scaled as follows: ����...
  • Page 6 78M6613 Hardware Design Guidelines AN_6613_049 2.4 Shunt Selection and Connections The 78M6613 sensor input range is ±12.5 μV (±8.84 μVrms) to ±250 mV (±176.78 mVrms). The value of the shunt to be used is usually a tradeoff between a higher shunt value to utilize the full analog sensor input range of the IC and the power loss in the shunt.

  • Page 7: Current Transformers

    AN_6613_049 78M6613 Hardware Design Guidelines 3 Isolated Configuration Alternatively, the 78M6613 can sense the load current using a current transformer (CT) for an isolated configuration. In this configuration, the 3.3 VDC supply rail (V3P3) for the 78M6613 is not directly tied to AC mains.

  • Page 8: Other Connections

    78M6613 Hardware Design Guidelines AN_6613_049 Figure 6 shows a basic connection diagram of a CT-based system. LINE RBurden 78M 6613 0.1µF 1000pF LOAD 0.1µF 0.1µF 1000pF V3P3 V3P3A 0.1µF 1000pF NEUTRAL Figure 6: Basic Connection Diagram of a CT-Based System The use of a CT allows for the 78M6613’s V3P3 to be isolated from the plant NEUTRAL wiring.

  • Page 9: Voltage Transformers

    AN_6613_049 78M6613 Hardware Design Guidelines 3.3 Voltage Transformers The pseudo-differential voltage measurement circuit of A2-A0 shown in Figure 6 can be replaced with a voltage transformer (VT). The VT replaces the two 2 MΩ resistor divider networks and requires use of only A0.

  • Page 10: Calibration Considerations

    78M6613 Hardware Design Guidelines AN_6613_049 4 Calibration Considerations All power measurement ICs can achieve higher accuracy by employing in-system calibration. In-system calibration compensates for the PCB trace lengths, LINE input voltage divider resistor network, current sensor tolerances and 78M6613 IC tolerances. Using tighter tolerance components can help reduce or even eliminate in-system calibration depending on the required measurement accuracy.

  • Page 11: Basic Configuration

    AN_6613_049 78M6613 Hardware Design Guidelines 5 Basic Configuration The following section covers the rest of the hardware interfaces found on the 78M6613. 5.1 Reset Circuitry The 78M6613 employs an active high Reset input pin. Figure 8 shows an external circuit configuration using a pushbutton switch to generate the reset signal, which may be useful during development.
  • Page 12 78M6613 Hardware Design Guidelines AN_6613_049 5.2 In Circuit Emulator (ICE) Pins The 78M6613 evaluation boards employ a reduced component ICE interface. This circuit design is sufficient when short ICE cables (less than 30 centimeters) are used or large RF fields are not present. If either case is not true, the following recommendations are to be utilized.
  • Page 13 AN_6613_049 78M6613 Hardware Design Guidelines 5.4 Driving External Loads Connect external loads to the digital outputs (DIO pins) as shown in Figure 11. V3P3 V3P3 V3P3D V3P3D GNDD GNDD 78M6613 78M6613 RECOMMENDED NOT RECOMMENDED Figure 11: Connecting an External Load to a Digital Output 5.5 Connecting I C EEPROMs Connect I...
  • Page 14 78M6613 Hardware Design Guidelines AN_6613_049 5.6 Connecting 3-Wire EEPROMs Connect µWire EEPROMs and other compatible devices to DIO pins DIO4 and DIO5 as shown in Figure 13. Connect DIO5 to both the DI and DO pins of the three-wire device. Connect the CS pin to a vacant 78M6613 DIO pin.
  • Page 15 AN_6613_049 78M6613 Hardware Design Guidelines 5.8 Power Supply Topologies Several power supply topologies are presented for consideration as a source of V3P3 power. 5.8.1 Capacitive Figure 15: Simple Circuit Design for Low-Power Applications 5.8.2 Transformer Figure 16: No High-Voltage Components for Higher Power Applications 5.8.3 Half-Wave Rectification with Switch-Mode Power Supply or Regulator Figure 17: High Efficiency for Higher Power Applications Rev.

  • Page 16: Timing Reference

    78M6613 Hardware Design Guidelines AN_6613_049 6 Timing Reference This section is both a design and troubleshooting guide for using the low-power crystal oscillator interface on the 78M6613. The 78M6613 typically uses a crystal oscillator as the clock source. Another option is to use an external canned oscillator.

  • Page 17: Component Placement

    AN_6613_049 78M6613 Hardware Design Guidelines 6.2 PCB Layout Recommendations 6.2.1 Power Supply Noise and Electromagnetic Noise Supply noise and electromagnetic noise are common causes of crystal oscillator failures. The oscillator gain, and the slow rise and fall times (the signal is near sinusoidal), are typical characteristics of a low-power and low-frequency oscillator.
  • Page 18 78M6613 Hardware Design Guidelines AN_6613_049 Figure 19: Crystal Y1 and Capacitors C7/C9 V3P3 Plane Figure 20: GND Shield Surrounds Crystal Traces Figure 21 shows the placement and layout of the crystal oscillator components on the same side of the PCB with the integrated circuit. There is a ground guard-ring surrounding the crystal oscillator. One way to accomplish this is by surrounding the circuit with a wide grounded trace.
  • Page 19 AN_6613_049 78M6613 Hardware Design Guidelines 6.3 Other Considerations 6.3.1 Solder Flux, Condensation and Other Conducting Materials A common cause of crystal oscillator malfunction is the buildup of contaminants on the PCB. PCB contaminants such as flux, humidity, finger prints etc. can create a high-impedance path from one of the oscillator pins to GND or the V3P3 supply preventing oscillator startup.
  • Page 20 78M6613 Hardware Design Guidelines AN_6613_049 32.768 kHz XOUT V3P3 Figure 22: Crystal Oscillator with Pull-up to Reduce Startup Time V3P3 PLANE / TOP LAYER MULTIPLE VIAS TO GND PLANE (BOTTOM LAYER) GNDD MULTIPLE VIAS TO GND PLANE (BOTTOM LAYER) Figure 23: Example of Layout of Crystal Oscillator with Pull-up Resistor 6.3.5 Temperature and Voltage Issues The crystal oscillator should be tested over the entire temperature and voltage range in which it is expected to operate.
  • Page 21 AN_6613_049 78M6613 Hardware Design Guidelines 6.3.6 Use with External Canned Oscillators The 78M6613 oscillator may be driven from an external 32.768 kHz clock source. The clock source can be derived from a canned oscillator or a divided down system clock. The external clock signal must be attenuated using the resistor divided shown in Figure 24.
  • Page 22 78M6613 Hardware Design Guidelines AN_6613_049 7 Hardware Design Checklist Verified Item Notes Non-isolated Configuration 3.3 VDC supply rail (V3P3) for the 78M6613 must be directly connected to AC-Neutral. Non-isolated Configuration Isolation components, if required, are added in between the measurement IC and the rest of the system.

  • Page 23: Revision History

    M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0  2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.

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