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Maxim Integrated 78M6612 Hardware Design Manuallines

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AN_6612_007
1 Introduction
This application note provides hardware and system design guidelines for those incorporating the
78M6612 system-on-chip (SoC) in their products. These guidelines will help hardware engineers to
reduce design cycle times.
The following topics are discussed:
•
Non-isolated Configuration
Safety Precautions
o
3.3 VDC Supply (V3P3) and System Connection
o
Line Voltage Resistor Divider Selection
o
Shunt Selection and Connections
o
•
Isolated Configuration
Current Transformers
o
Other Connections
o
Voltage Transformers
o
•
Calibration Considerations
•
Basic Configuration
Reset Circuitry
o
V2P5 Voltage Reference Pin
o
V1 Pin
o
In Circuit Emulator (ICE) Pins
o
Connecting 5 V Devices
o
Driving External Loads
o
Connecting I2C EEPROMs
o
Connecting 3-Wire EEPROMs
o
UART0 (TX/RX)
o
UART1 Interface
o
Power Supply Topologies
o
•
Timing Reference
Oscillator Connections and Components Selection
o
PCB Layout Recommendations
o
Other Considerations
o
A Hardware Design Checklist is provided at the end of this document as a quick summary.
Rev 2
Hardware Design Guidelines
APPLICATION NOTE
78M6612
November 2011
1

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Summary of Contents for Maxim Integrated 78M6612

  • Page 1 November 2011 1 Introduction This application note provides hardware and system design guidelines for those incorporating the 78M6612 system-on-chip (SoC) in their products. These guidelines will help hardware engineers to reduce design cycle times. The following topics are discussed: •...

  • Page 2: Safety Precautions

    When using a resistive shunt current sensor, the measurement IC and its power domain are not isolated from the AC mains. In this configuration, the 3.3 VDC supply rail (V3P3) for the 78M6612 must be directly connected to AC-Neutral for precision energy measurement. Isolation components, if required, are added in between the measurement IC and the rest of the system.
  • Page 3 2.2 3.3 VDC Supply (V3P3) and System Connection The 78M6612 requires a single 3.3 VDC supply. The 3.3 VDC (V3P3) also represents the reference potential for the 78M6612. The basic connections for a shunt-based system are represented in Figure 1.
  • Page 4 Effective 3.3 VDC bypassing incorporates the combination of three different capacitor values. A 1000 pF in parallel with a 0.1 µF ceramic capacitor must be placed as close as possible to the 78M6612 V3P3A pin. Place the 1000 pF capacitor should be placed closest to the V3P3A pin of the 78M6612. An additional 22 µF bulk capacitor is placed in the vicinity of the V3P3SYS pin to provide decoupling for the...
  • Page 5 78M6612 Hardware Design Guidelines 2.3 Line Voltage Resistor Divider Selection The input line voltage must be scaled to match the 78M6612’s ADC input signal range of 176.78 mVrms. In the example of Figure 3, the line voltage is scaled as follows: The use of two 1 MΩ...
  • Page 6 2.4 Shunt Selection and Connections The 78M6612 sensor input range is 12.5 μV (8.84 μVrms) to +250 mV (176.78 mVrms). The value of the shunt to be used is usually a tradeoff between a higher shunt value to utilize the full analog sensor input range of the IC and the power loss in the shunt.

  • Page 7: Current Transformers

    Alternatively, the 78M6612 can sense the load current using a current transformer (CT) for an isolated configuration. In this configuration, the 3.3 VDC supply rail (V3P3) for the 78M6612 is not directly tied to AC mains. The analog inputs to the 78M6612 are used as follows: •...

  • Page 8: Other Connections

    Figure 6: Basic Connection Diagram of a CT-Based System The use of a CT allows for the 78M6612’s V3P3 to be isolated from the plant NEUTRAL wiring. This topology eliminates the safety issues stated earlier regarding shunt-based current sensing. Figure 6 shows a 2 MΩ...

  • Page 9: Voltage Transformers

    VT provides accurate linear measurements from 100VAC to 240VAC. The basic connection of a VT to the 78M6612 is similar to Figure 5. The VT’s secondary output voltage range in conjunction with the manufacturer’s recommended burden resistor value must meet the 78M6612’s signal input range of ±176.78 mVrms (±250 mVpk).

  • Page 10: Calibration Considerations

    All power measurement ICs must employ in-system calibration to achieve higher accuracy. In-system calibration compensates for the PCB trace lengths, LINE input voltage divider resistor network, current sensor tolerances, and 78M6612 IC tolerances. Using tighter tolerance components can help reduce or even eliminate in-system calibration depending on the required measurement accuracy.

  • Page 11: Basic Configuration

    This section describes the configuration of the remaining hardware interfaces found on the 78M6612. 5.1 Reset Circuitry The 78M6612 employs an active high Reset input pin. Figure 7 shows the external circuit configuration using a pushbutton switch to generate the reset signal. If an external reset is not required, connect the Reset pin to GND (GNDD).
  • Page 12 (via an external battery attached to the VBAT pin). Connect the voltage divider shown in Figure 9 to the V1 pin to enable normal (WDT enabled) 78M6612 operation. The watchdog may be disabled for debugging by raising the V1 pin above 2.9 V.
  • Page 13 5.5 Connecting 5 V Devices All digital input pins (DIO pins) of the 78M6612 are 5 V compatible allowing connection to external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V devices.
  • Page 14 78M6612 Hardware Design Guidelines AN_6612_007 5.6 Driving External Loads Connect external loads to the digital outputs (DIO pins) as shown in Figure 11. V3P3 V3P3 DGND DGND RECOMMENDED NOT RECOMMENDED Figure 12: Connecting an External Load to a Digital Output 5.7 Connecting I...

  • Page 15: Uart1 Interface

    Figure 13. Connect DIO5 to both the DI and DO pins of the three-wire device. Connect the CS pin to a vacant 78M6612 DIO pin. Add a pull-up resistor of roughly 10 kΩ to V3P3 to the DI/DO signals. Add a pull-down resistor to the CS pin to prevent that the 3-wire device from being enabled on power-up before the 78M6612 can establish a stable signal for CS.
  • Page 16 78M6612 Hardware Design Guidelines AN_6612_007 5.11 Power Supply Topologies Several power supply topologies are presented for consideration as a dedicated source of V3P3 power in non-isolated configurations. 5.11.1 Capacitive Figure 16: Simple Circuit Design for Low-Power Applications 5.11.2 Transformer NEUTRAL...

  • Page 17: Timing Reference

    This section is both a design and troubleshooting guide for using the low-power crystal oscillator interface on the 78M6612. The 78M6612 typically uses a crystal oscillator as the clock source. Another option is to use an external canned oscillator. The main advantages of a crystal oscillator are frequency accuracy, stability, low cost, high reliability, and low power consumption.

  • Page 18: Component Placement

    21 show the placement and layout of the crystal oscillator components on the opposite side of the PCB from the 78M6612. The 32.768 kHz crystal and its two 27 pF capacitors are placed on the GND layer. This allows the crystal and the two capacitors to be surrounded with a ground shield. Place the XIN and XOUT vias as close as possible to the 78M6612 pins.
  • Page 19 AN_6612_007 78M6612 Hardware Design Guidelines Figure 20: Crystal Y1 and Capacitors C7/C9 V3P3 Plane GND Shield Figure 21: GND Shield Surrounds Crystal Traces Figure 21 shows the placement and layout of the crystal oscillator components on the same side of the PCB with the integrated circuit (a 78M6613 is used in the example).
  • Page 20 GND or the V3P3 supply preventing oscillator startup. To overcome this problem, check for contaminant accumulation between the crystal leads and beneath the 78M6612 package. Board cleanliness is most critical when using water soluble solder paste.
  • Page 21 6.3.6 Use with External Canned Oscillators The 78M6612 oscillator may be driven from an external 32.768 kHz clock source. The clock source can be derived from a canned oscillator or a divided down system clock. The external clock signal must be attenuated using the resistor divided shown in Figure 25.
  • Page 22 78M6612 Hardware Design Guidelines AN_6612_007 +3.3V External Canned Oscillator 32.768 kHz Clock Divider XOUT XIN Attenuator Figure 25: 78M6612 with External Canned Oscillator Rev 2...
  • Page 23 7 Hardware Design Checklist Verified Item Notes Non-isolated Configuration 3.3 VDC supply rail (V3P3) for the 78M6612 must be directly connected to AC-Neutral. Non-isolated Configuration Isolation components, if required, are added in between the measurement IC and the rest of the system.

  • Page 24: Revision History

    78M6612 Hardware Design Guidelines AN_6612_007 Revision History REVISION REVISION DESCRIPTION NUMBER DATE 3/23/2010 First publication. 8/30/2010 Added the Timing Reference section; fixed VB connection in Figure 1. Added “The V3P3 connection to AC-Neutral can be eliminated when using current transformers (CT) as the current sensing elements. Refer to the section on Isolated Connections for designing with CTs.”...

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