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Maxim Integrated Teridian 78M6618 Hardware Design Manuallines

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A Maxim Integrated Products Brand
AN_6618_027
1 Introduction
This application note provides hardware and system design guidelines for those incorporating the
78M6618 System on Chip in their products. These guidelines will help hardware engineers to reduce
design cycle times.
The following topics are discussed:
•
Non-isolated Configuration
Safety Precautions
o
3.3 VDC Supply (V3P3) and System Connection
o
Line Voltage Resistor Divider Selection
o
Shunt Selection and Connections
o
•
Isolated Configuration
Current Transformers
o
Other Connections
o
Voltage Transformers
o
•
Calibration Considerations
•
Basic Configuration
Reset Circuitry
o
V2P5 Voltage Reference Pin
o
V1 Pin
o
In Circuit Emulator (ICE) Pins
o
Connecting 5 V Devices
o
Driving External Loads
o
Connecting I2C EEPROMs
o
Connecting 3-Wire EEPROMs
o
UART0 (TX/RX)
o
UART1 Interface
o
Power Supply Topologies
o
•
Timing Reference
Oscillator Connections and Components Selection
o
PCB Layout Recommendations
o
Other Considerations
o
Rev. 1.2
Hardware Design Guidelines
© 2010 Teridian Semiconductor Corporation
78M6618
APPLICATION NOTE
October 2010
1

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Summary of Contents for Maxim Integrated Teridian 78M6618

  • Page 1 78M6618 Hardware Design Guidelines A Maxim Integrated Products Brand APPLICATION NOTE AN_6618_027 October 2010 1 Introduction This application note provides hardware and system design guidelines for those incorporating the 78M6618 System on Chip in their products. These guidelines will help hardware engineers to reduce design cycle times.

  • Page 2: Safety Precautions

    78M6618 Hardware Design Guidelines AN_6618_027 2 Non-isolated Configuration When using a resistive shunt current sensor, the measurement IC and its power domain are not isolated from the AC mains. In this configuration, the 3.3 VDC supply rail (V3P3) for the 78M6618 must be directly connected to AC-Neutral for precision energy measurement.
  • Page 3 AN_6618_027 78M6618 Hardware Design Guidelines 2.2 3.3 VDC Supply (V3P3) and System Connection The 78M6618 requires a single 3.3 VDC supply. The 3.3 VDC (V3P3) also represents the reference potential for the 78M6618. The basic connections for a shunt-based system are represented in Figure 1. LINE 78M6618 0.1uF...
  • Page 4 78M6618 Hardware Design Guidelines AN_6618_027 Effective 3.3 VDC bypassing incorporates the combination of three different capacitor values. A 1000 pF in parallel with a 0.1 µF ceramic capacitor must be placed as close as possible to the 78M6618 V3P3A pin. Place the 1000 pF capacitor closest to the V3P3A pin of the 78M6618. An additional 22 µF bulk capacitor is placed in the vicinity of the V3P3SYS pin to provide decoupling for the external DIO circuitry.
  • Page 5 AN_6618_027 78M6618 Hardware Design Guidelines 2.3 Line Voltage Resistor Divider Selection The input line voltage must be scaled to match the 78M6618’s ADC input signal range of 176.78 mVrms. In the example of Figure 3, the line voltage is scaled as follows: The use of two 1 MΩ...
  • Page 6 78M6618 Hardware Design Guidelines AN_6618_027 2.4 Shunt Selection and Connections The 78M6618 sensor input range is 12.5 μV (8.84 μVrms) to +250 mV (176.78 mVrms). The value of the shunt to be used is usually a tradeoff between a higher shunt value to utilize the full analog sensor input range of the IC and the power loss in the shunt.
  • Page 7 AN_6618_027 78M6618 Hardware Design Guidelines 2.4.1 Single-ended Shunt Connections Multi-shunt measurement systems typically require use of differential input circuits. These differential input circuits add cost due to added components. The 78M6618 Evaluation Board presents a lower cost multi-shunt measurement system alternative. Additionally, the proposed circuit design results in a very compact printed board layout for a high accuracy energy measurement system.
  • Page 8 78M6618 Hardware Design Guidelines AN_6618_027 This represents a 0.1% error when using a 6 mohm shunt. Current does not flow in a single straight line between two points in a conductor. Due to internal resistance in the conductor, the current spreads out through the medium. Figure 6 shows how current from one outlet produces a distributive voltage across the copper disk.

  • Page 9: Current Transformers

    AN_6618_027 78M6618 Hardware Design Guidelines 3 Isolated Configuration Alternatively, the 78M6618 can sense the load current using a current transformer (CT) for an isolated configuration. In this configuration, the 3.3 VDC supply rail (V3P3) for the 78M6618 is not directly tied to AC mains.

  • Page 10: Other Connections

    78M6618 Hardware Design Guidelines AN_6618_027 Figure 8 shows a basic connection diagram of a CT-based system. LINE Rburden 78M6618 750 x8 1000pF IA-IH LOAD 1000pF 0.1μF 0.1μF V3P3 Unused Current Inputs 1000pF NEUTRAL Figure 8: Basic Connection Diagram of a CT-Based System The use of a CT allows for the 78M6618’s V3P3 to be isolated from the plant NEUTRAL wiring.

  • Page 11: Voltage Transformers

    AN_6618_027 78M6618 Hardware Design Guidelines 3.3 Voltage Transformers The pseudo-differential voltage measurement circuit of VB-VA shown in Figure 6 can be replaced with a voltage transformer (VT). The VT replaces the two 2 MΩ resistor divider networks and requires use of only V.

  • Page 12: Calibration Considerations

    78M6618 Hardware Design Guidelines AN_6618_027 4 Calibration Considerations All power measurement ICs must employ in-system calibration to achieve higher accuracy. In-system calibration compensates for the PCB trace lengths, LINE input voltage divider resistor network, current sensor tolerances and 78M6618 IC tolerances. Using tighter tolerance components can help reduce or even eliminate in-system calibration depending on the required measurement accuracy.

  • Page 13: Basic Configuration

    AN_6618_027 78M6618 Hardware Design Guidelines 5 Basic Configuration The section describes the remaining hardware interfaces found on the 78M6618. 5.1 Reset Circuitry The 78M6618 employs an active high Reset input pin. Figure shows the external circuit configuration using a pushbutton switch to generate the reset signal. If an external reset is not required, connect the Reset pin to GND (GNDD).
  • Page 14 78M6618 Hardware Design Guidelines AN_6618_027 5.3 V1 Pin The V1 pin is connected to an internal power-fail comparator. The V1 input voltage is compared to an internal reference voltage of 1.6 V (VBIAS). If the V1 voltage is above VBIAS, the comparator output is high (1) signaling normal operation.
  • Page 15 AN_6618_027 78M6618 Hardware Design Guidelines 5.4 In Circuit Emulator (ICE) Pins The 78M6618 evaluation boards employ a reduced component ICE interface. This circuit design is sufficient when short ICE cables (less than 12 inches) are used or large RF fields are not present. If either case is not true, the following recommendations are to be utilized.
  • Page 16 78M6618 Hardware Design Guidelines AN_6618_027 5.6 Driving External Loads Connect external loads to the digital outputs (DIO pins) as shown in Figure 8. V3P3 V3P3 DGND DGND RECOMMENDED NOT RECOMMENDED Figure 8: Connecting an External Load to a Digital Output 5.7 Connecting I C EEPROMs Connect I...

  • Page 17: Uart1 Interface

    AN_6618_027 78M6618 Hardware Design Guidelines 5.8 Connecting 3-Wire EEPROMs Connect µWire EEPROMs and other compatible devices to DIO pins DIO4 and DIO5 as shown in Figure 10. Connect DIO5 to both the DI and DO pins of the three-wire device. Connect the CS pin to a vacant 78M6618 DIO pin.
  • Page 18 78M6618 Hardware Design Guidelines AN_6618_027 5.11 Power Supply Topologies Several power supply topologies are presented for consideration as a dedicated source of V3P3 power in non-isolated configurations. 5.11.1 Capacitive Figure 12: Connections for the RX Pin 5.11.2 Transformer NEUTRAL VREG V3P3 78M6618 LIVE...

  • Page 19: Timing Reference

    AN_6618_027 78M6618 Hardware Design Guidelines 6 Timing Reference This section is both a design and troubleshooting guide for using the low-power crystal oscillator interface on the 78M6618. The 78M6618 typically uses a crystal oscillator as the clock source. Another option is to use an external canned oscillator.

  • Page 20: Component Placement

    78M6618 Hardware Design Guidelines AN_6618_027 6.2 PCB Layout Recommendations 6.2.1 Power Supply Noise and Electromagnetic Noise Supply noise and electromagnetic noise are common causes of crystal oscillator failures. The oscillator gain, and the slow rise and fall times (the signal is near sinusoidal), are typical characteristics of a low-power and low-frequency oscillator.
  • Page 21 AN_6618_027 78M6618 Hardware Design Guidelines Figure 16: Crystal Y1 and Capacitors C7/C9 V3P3 Plane GND Shield Figure 17: GND Shield Surrounds Crystal Traces Figure 18 shows the placement and layout of the crystal oscillator components on the same side of the PCB with the integrated circuit (a 78M6613 is used in the example).
  • Page 22 78M6618 Hardware Design Guidelines AN_6618_027 6.3 Other Considerations 6.3.1 Solder Flux, Condensation and Other Conducting Materials A common cause of crystal oscillator malfunction is the buildup of contaminants on the PCB. PCB contaminants such as flux, humidity, finger prints etc. can create a high-impedance path from one of the oscillator pins to GND or the V3P3 supply preventing oscillator startup.
  • Page 23 AN_6618_027 78M6618 Hardware Design Guidelines 32.768 kHz XOUT V3P3 Figure 19: Crystal Oscillator with Pull-up to Reduce Startup Time V3P3 PLANE / TOP LAYER MULTIPLE VIAS TO GND PLANE (BOTTOM LAYER) GNDD MULTIPLE VIAS TO GND PLANE (BOTTOM LAYER) Figure 20: Example of Layout of Crystal Oscillator with Pull-up Resistor 6.3.5 Temperature and Voltage Issues The crystal oscillator should be tested over the entire temperature and voltage range in which it is expected to operate.
  • Page 24 78M6618 Hardware Design Guidelines AN_6618_027 6.3.6 Use with External Canned Oscillators The 78M6618 oscillator may be driven from an external 32.768 kHz clock source. The clock source can be derived from a canned oscillator or a divided down system clock. The external clock signal must be attenuated using the resistor divided shown in Figure 7.
  • Page 25 AN_6618_027 78M6618 Hardware Design Guidelines 7 Hardware Design Checklist Verified Item Notes Non-isolated Configuration 3.3 VDC supply rail (V3P3) for the 78M6618 must be directly connected to AC-Neutral. Non-isolated Configuration Isolation components, if required, are added in between the measurement IC and the rest of the system.

  • Page 26: Revision History

    78M6618 Hardware Design Guidelines AN_6618_027 Revision History Revision Date Description 4/16/2010 First publication. 8/31/2010 Added the Timing Reference section. 10/29/2010 Added Section 3.3, Voltage Transformers. Rev 1.2...

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