EMAC PRIMER Instruction Manual page 17

operates with.
Capacitor C9, and several other capacitors spread about the board provide D.C. power supply bypass. These bypass
capacitors stabilize the power supply voltage fed to the logic devices on the PRIMER.
To understand the speaker circuit, remember that as described earlier, the SYSCLK signal is first divided by ten, and fed to
the 8155 timer input. The timer's output goes to the 8085's RST 7.5 interrupt input, and to an AND gate that drives a piezo-
electric speaker element. The piezo-electric speaker has a limited frequency range, but many useful sounds can still be
produced by appropriate setting of the timer's divide ratio, and turning the output on and off through the 8085's SOD signal.
The SYSCLK frequency of 3.072 MHZ is divided down by U12 to 307.2 KHZ, then fed to the timer input of the 8155. By
setting the timer's divide ratio from 2 to 16383 ( in software ), the range of frequencies can be from 153.6 KHZ down to
18.75 Hz.
Also shown on this sheet, are the spare gates that are not used by the PRIMER circuit, but present on the board. This
often occurs since gate packages often come with multiple gates on one chip. As is customary, unused gate inputs should
be defined to an idle logic state to prevent random oscillations, latchup, etc. This is done primarily for CMOS and NMOS
devices, because TTL gates usually have built-in pullups on their inputs.
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