Sherwood RD-7502 Service Manual page 39

GP0[4](EXT_INT4)/AMUTEIN1 1
GP0[6](EXT_INT6) 2
CV 3
DD
4
GP0[5](EXT_INT5)/AMUTEIN0
GP0[7](EXT_INT7) 5
DV 6
DD
V 7
SS
CV
8
DD
AHCLKX0 9
CV 10
DD
V 11
SS
ACLKX0 12
ACLKR0 13
14
AXR0[1]/AXR1[14]
AFSX0 15
AFSR0 16
17
DV
DD
AXR0[0]/AXR1[15] 18
V 19
SS
FSX1 20
DX1 21
CLKX1 22
V 23
SS
24
CV
DD
DR1 25
V 26
SS
CV 27
DD
CV 28
DD
DV 29
DD
V 30
SS
CV 31
DD
DV 32
DD
V 33
SS
34
V
SS
CV 35
DD
V 36
SS
EMIF8
[DA607
ONLY]
McASP1
(10
Serializers)
McASP0
(10
Serializers)
McBSP1
(SPI Only)
Timer 1
Timer 0
GP1
GP0
In addition to fixed-point instructions, these functional units execute floating-point instructions.
EMIF8 interfaces to:
- SDRAM
- SRAM
- ROM/Flash
- I/O devices
TMS320DA607 : IC805
DA607 and DA605 Digital Signal Processors
L2 Cache/
Memory
4 Banks
64K Bytes
Total
(4-Way)
[DA607
ONLY]
Data Path A
A Register File
L2
Enhanced
†
Memory .L1 .S1 .M1
DMA
Controller
DA607:
(16
128K Bytes
Channels)
DA605:
192K Bytes
Clock Generator and PLL
x4 through x25 Multipliers
/1 through /32 Dividers
R2 ROM
512K
Bytes
Total
McBSP interfaces to: McASPs interface to:
- SPI Control Port - I2S Multichannel ADC, DAC, Codec, DIR
- Serial EEPROM - DIT : Multiple Outputs
38
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
L1P Cache
Direct Mapped
4K Bytes Total
C67x™ CPU
Instruction Fetch
Control
Registers
Instruction Dispatch
Control
Instruction Decode
Logic
Data Path B
Test
B Register File
In-Circuit
Emulation
Interrupt
† † † † †
.D1 .D2 .M2 .S2 .L2
Control
L1D Cache
2-Way Set
Associative
4K Bytes Total
Power-Down
Logic
GP0[0]
AFSX1
V
SS
AMUTE1
CV
DD
DV
DD
ACLKX1
CV
DD
AXR0[8]/AXR1[7]
AXR0[9]/AXR1[6]
AXR0[10]/AXR1[5]
AXR0[11]/AXR1[4]
V
SS
AXR0[12]/AXR1[3]
AXR0[13]/AXR1[2]
CV
DD
AXR0[14]/AXR1[1]
AXR0[15]/AXR1[0]
DV
DD
ACLKR1
AFSR1
V
SS
CV
DD
RSV
ED0/GP1[0]
ED1/GP1[1]
ED2/GP1[2]
ED3/GP1[3]
ED5/GP1[5]
ED4/GP1[4]
V
SS
CV
DD
ED7/GP1[7]
ED6/GP1[6]
DV
DD
BE0