Sherwood RD-7502 Service Manual page 35

No. Pin Name I/O
40 NC
41 ROUT3 O
42 NC
43 LOUT2 O
44 NC
45 ROUT2 O
46 NC
47 LOUT1 O
48 NC
49 ROUT1 O
50 NC
51 LIN
52 RIN
53 VCOM
54 VREFH
55 AVDD -
56 AVSS -
57 RX0 I
58 NC -
59 RX1 I
60 TEST1 I
61 RX2 I
62 NC -
63 RX3 I
64 PVSS -
65 R -
66 PVDD -
67 RX4 I
68 TEST2 I
69 RX5 I
70 CAD0 I
71 RX6 I
72 CAD1 I
73 RX7 I
74 I2C I
75 DAUX2 I
76 VIN I
77 MCLK I
78 TX0 O
79 TX1 O
80 INT0 O
Note : All input pins except internal biased pins and internal pull-down pin should not be left floating.
No Connect pin
-
No internal bonding. This pin should be opened.
DAC3 Rch Analog Output Pin
No Connect pin
-
No internal bonding. This pin should be opened.
DAC2 Lch Analog Output Pin
No Connect pin
-
No internal bonding. This pin should be opened.
DAC2 Rch Analog Output Pin
No Connect pin
-
No internal bonding. This pin should be opened.
DAC1 Lch Analog Output Pin
No Connect pin
-
No internal bonding. This pin should be opened.
DAC1 Rch Analog Output Pin
No Connect pin
-
No internal bonding. This pin should be opened.
I Lch Analog Input Pin
I Rch Analog Input Pin
Common Voltage Output Pin
-
2.2µF capacitor should be connected to AVSS externally.
Positive Voltage Reference Input Pin, AVDD
-
Analog Power Supply Pin, 4.5V~ 5.5V
Analog Ground Pin, 0V
Receiver Channel 0 Pin (Internal biased pin. Internally biased at PVDD/2)
No Connect pin
No internal bonding. This pin should be connected to PVSS.
Receiver Channel 1 Pin (Internal biased pin. Internally biased at PVDD/2)
Test 1 Pin
This pin should be connected to PVSS.
Receiver Channel 2 Pin (Internal biased pin. Internally biased at PVDD/2)
No Connect pin
No internal bonding. This pin should be connected to PVSS.
Receiver Channel 3 Pin (Internal biased pin. Internally biased at PVDD/2)
PLL Ground pin
External Resistor Pin
12kΩ +/-1% resistor should be connected to PVSS externally.
PLL Power supply Pin, 4.5V~ 5.5V
Receiver Channel 4 Pin (Internal biased pin. Internally biased at PVDD/2)
Test 2 Pin
This pin should be connected to PVSS.
Receiver Channel 5 Pin (Internal biased pin. Internally biased at PVDD/2)
Chip Address 0 Pin (ADC/DAC part)
Receiver Channel 6 Pin (Internal biased pin. Internally biased at PVDD/2)
Chip Address 1 Pin (ADC/DAC part)
Receiver Channel 7 Pin (Internal biased pin. Internally biased at PVDD/2)
Control Mode Select Pin.
"L": 4-wire Serial, "H": I
Auxiliary Audio Data Input Pin (DIR/DIT part)
V-bit Input Pin for Transmitter Output
Master Clock Input Pin
Transmit Channel (Through Data) Output 0 Pin
Transmit Channel Output1 pin
When TX bit = "0", Transmit Channel (Through Data) Output 1 Pin.
When TX bit = "1", Transmit Channel (DAUX2 Data) Output Pin (Default).
Interrupt 0 Pin
Function
2
C Bus
34