Sherwood RD-7502 Service Manual page 34

No. Pin Name I/O
1 INT1 O
BOUT
O
2
3 TVDD
4 DVDD
5 DVSS
6 XTO O
7 XTI
8 TEST3
9 MCKO2 O
10 MCKO1 O
11 COUT O
12 UOUT O
13 VOUT O
14 SDTO2 O
15 BICK2 I/O
16 LRCK2 I/O
17 SDTO1 O
18 BICK1 I/O
19 LRCK1 I/O
20 CDTO O
CCLK
21
SCL
CDTI
22
SDA I/O
23 CSN
24 DAUX1
25 SDTI4
26 SDTI3
27 SDTI2
28 SDTI1
29 XTL1
30 XTL0
31 PDN
32 MASTER
DZF2 O
33
OVF O
34 DZF1 O
35 LOUT4 O
36 NC
3 7
ROUT4 O
38 NC
39 LOUT3 O
Interrupt 1 Pin
Block-Start Output Pin for Receiver Input
"H" during first 40 flames.
-
Output Buffer Power Supply Pin, 2.7V~5.5V
-
Digital Power Supply Pin, 4.5V~5.5V
- Digital Ground Pin
X'tal clock Output Pin
I X'tal / External clock Input Pin
Test 3 Pin
I
This pin should be connected to DVSS.
Master Clock Output 2 Pin
Master Clock Output 1 Pin
C-bit Output Pin for Receiver Input
U-bit Output Pin for Receiver Input
V-bit Output Pin for Receiver Input
Audio Serial Data Output Pin (DIR/DIT part)
Audio Serial Data Clock Pin (DIR/DIT part)
Channel Clock Pin (DIR/DIT part)
Audio Serial Data Output Pin (ADC/DAC part)
Audio Serial Data Clock Pin (ADC/DAC part)
Input Channel Clock Pin
Control Data Output Pin in Serial Mode, I2C pin= "L".
I Control Data Clock Pin in Serial Mode, I2C pin= "L"
I Control Data Clock Pin in Serial Mode, I2C pin= "H"
I Control Data Input Pin in Serial Mode, I2C pin= "L".
Control Data Pin in Serial Mode, I2C pin= "H".
I Chip Select Pin in Serial Mode, I2C pin="L".
I This pin should be connected to DVSS, I2C pin="H".
I AUX Audio Serial Data Input Pin (ADC/DAC part)
I DAC4 Audio Serial Data Input Pin
I DAC3 Audio Serial Data Input Pin
I DAC2 Audio Serial Data Input Pin
I DAC1 Audio Serial Data Input Pin
I X'tal Frequency Select 0 Pin
I X'tal Frequency Select 1 Pin
Power-Down Mode Pin
I When "L", the AK4588 is powered-down, all output pin goes "L", all registers are
reset. When CAD1-0 pins are changed, the AK4588 should be reset by PDN pin.
Master Mode Select Pin
I
"H": Master mode, "L": Slave mode
Zero Input Detect 2 Pin
When the input data of the group 1 follow total 8192 LRCK cycles with "0" input
data, this pin goes to "H". When RSTN1 bit is "0" or PWDAN bit is "0", this pin
goes to "H".
Analog Input Overflow Detect Pin
This pin goes to "H" if the analog input of Lch or Rch overflows. This pin becomes
OVF pin if OVFE bit is set to 1.
Zero Input Detect 1 Pin
When the input data of the group 1 follow total 8192 LRCK cycles with "0" input
data, this pin goes to "H". When RSTN1 bit is "0" or PWDAN bit is "0", this pin goes
to "H".
DAC4 Lch Analog Output Pin
No Connect pin
-
No internal bonding. This pin should be opened.
DAC4 Rch Analog Output Pin
No Connect pin
-
No internal bonding. This pin should be opened.
DAC3 Lch Analog Output Pin
Function
(Table 13)
(Table 13)
33