Switching The Two Counting Channels In Parallel; Interrupts - Siemens SMP16-SFT251 Technical Description

SMP16-SFT251
6.3.12

Switching the Two Counting Channels in Parallel

The two counters can be switched in parallel (i.e., track signals A, B and N of counting channel 0 can
be switched to the counter of counting channel 1). However, this leaves the track signals of counting
channel 1 without any function. This setting requires that bit K02K1 be set in control register 2 (bit 7).
See chapter 6.4.4.
Special signals ZS00, ZS10 and ZS20 of counting channel 0 can be connected to counting channel 1.
This can then be used to trigger the universal registers of counting channel 1 with the special signals
of channel 1 and channel 0. For the assignment of signals ZS00 to ZS20 to the individual universal
registers and the activation of this parallel circuit, see the description of control register 2
(chapter 6.4.4).
6.3.13

Interrupts

The following interrupts are available.
Interrupt Source
INT0 Zero-marking pulse of
channel 0 or channel 1
INT1 Rising edge on ZS00, ZS20,
ZS01 or ZS21
INT2 Rising edge on
ZS10 or ZS30
or
Overflow CB0 of counter
channel 0
INT3 Rising edge on
ZS11 or ZS31
or
Overflow CB1 of
counter channel 1
INT4 Comparator of counting
channel 0
INT5 Comparator of counting
channel 1
1) The clear register is described in more detail in chapter 6.4.10.
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(4)J31069-D2090-U001-A1-7618
1)
Reset
Read the applicable zero-
marking-pulse buffer
Or in the clear register:
Bit 0 (CLR_INT0_0) = "1"
or
Bit 8 (CLR_INT0_1) = "1"
"Reset alarm bits" command
Or in clear register:
Bit 1 (CLR_INT1_00) = "1,"
Bit 2 (CLR_INT1_20) = "1,"
Bit 9 (CLR_INT1_01) = "1,"
or
Bit 10 (CLR_INT1_21) = "1"
In clear register:
Bit 3 (CLR_INT2_10) = "1,"
Bit 4 (CLR_INT2_30) = "1,"
or
Bit 5 (CLR_INT2_CB0) = "1"
In clear register:
Bit 11 (CLR_INT3_11) = "1,"
Bit 12 (CLR_INT3_31) = "1,"
or
Bit 13 (CLR_INT3_CB1) = "1"
In clear register:
Bit 6 (CLR_INT4_CR0) = "1"
In clear register:
Bit 14 (CLR_INT5_CR1) = "1"
Programming the Board
Masking Status Bits
Bit 7 (channel 0) Bit 0 of the INT
and registers of
Bit 6 (channel 1) channel 0 or
in control register channel 1 or
0 bit 0 (channel 0)
and bit 1
(channel 1) in
status register 0
Bit 5 (LAX) of Bits 4 to 7 in
status register 0
control register 0
(for all signals)
Bits 0 to 2 in Bits 0 to 2 in
interrupt mask status register 2
Bits 8 to 10 in Bits 8 to 10 in
interrupt mask status register 2
Bit 3 in interrupt Bit 3 in status
mask register 2
Bit 11 in interrupt Bit 11 in status
mask register 2
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