Table of Contents .......................................................................................................................... 2-3
Section 1 Contents ............................................................................................................................4
Figure 1. Scope Photo of Boot Prompt at J5 Pin 11 ..........................................................................7
Figure 2. Cable for Amplifier Output Connection at J701 .................................................................. 8
Figure 3. Output Wire Connection View at J701 ...............................................................................8
Figure 4. Input Wire Connection View at J700 .................................................................................. 9
Figure 5. Triac Jumping View on DSP PCB .....................................................................................10
Amplifier Test Procedures ..............................................................................................................12
Figure 6. Codec to DSP, Digital Audio Signal Path ..........................................................................17
Figure 7. Micro to/from DSPs ..........................................................................................................17
Figure 8. DSP PCB Test Point Locations Layout Diagram, Solder Side ..........................................19
Scope Photos ............................................................................................................................ 20-21
Figure 9. Codec (U100) Scope Photo, Mute Condition ...................................................................20
Figure 10. Microcontroller (U202) Scope Photo, Power Up ............................................................21
Figure 11. Microcontroller 8 MHz clock at U202 pin 39 ...................................................................21
Section 2 Contents ..........................................................................................................................22
Test Setup Procedures ...................................................................................................................24
Figure 12. Scope Photo of Boot Prompt at J5 Pin 11......................................................................26
Figure 13. Codec to DSP, Digital Audio Signal Path ........................................................................32
Figure 14. Micro to/from DSPs ........................................................................................................32
DSP PCB Troubleshooting ..............................................................................................................34
Figure 15. DSP PCB Test Point Locations Layout Diagram, Solder Side ........................................34
Scope Photos ............................................................................................................................ 35-41
Figure 16. Codec (U100) Scope Photo, Un-mute Condition ...........................................................35
Figure 17. Codec (U100) Scope Photo, Mute Condition ................................................................. 36
Figure 18. Microcontroller (U202) Scope Photo, Power Up ............................................................37
Figure 19. SPDIF Signal at U100 pin 42 .........................................................................................38
Figure 20. Microcontroller 8 MHz clock at U202 pin 39 ...................................................................38
Figure 21. Codec 11.2896 MHz Clock ............................................................................................39
Figure 22. 40 MHz DSP clock .........................................................................................................39
Figure 23. 3.3V Switching Power Supply Signals............................................................................40
Figure 24. Power Up Condition at U202 Pin 25 ...............................................................................40
Figure 25. Transmit Frame Sync .....................................................................................................41
Figure 26. Serial Data Clock ...........................................................................................................41
Figure 27. Audio Data .....................................................................................................................41
Section 3 Contents ..........................................................................................................................42
Test Setup Procedure .....................................................................................................................43
Table of Contents
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