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ON Semiconductor AX5045 Programming Manual

Ultra-low power narrow-band sub ghz (60−1050 mhz) rf transceiver with integrated +23 dbm high power amplifier
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AND9902/D
AX5045 Programming
Manual
Ultra-Low Power Narrow-Band Sub GHz
(60−1050 MHz) RF Transceiver with
Integrated +23 dBm High Power Amplifier

OVERVIEW

AX5045 is a true single chip low-power CMOS
transceiver for narrow band applications. A fully integrated
VCO support most carrier frequencies from 60 MHz to
1050 MHz. The on-chip transceiver consists of a fully
integrated RF front-end with modulator, and demodulator.
Base band data processing is implemented in an advanced
and flexible communication controller that enables user
friendly communication via the SPI interface.
5
RX_P
LNA
6
RX_N
TX_P
3
PA
TX_N
4
VCHOKE
27
VDD_IO
1,23
Crystal
Oscillator
Divider
typ.
16 MHz
27
28
© Semiconductor Components Industries, LLC, 2019
March, 2021 − Rev. 1
AX5045
25
26
Mixer
IF Filter &
AGC PGAs
AGC
F
OUT
RF Frequency
F
XTAL
Generation
Subsystem
RF Output
60 MHz –
1.05 GHz
13
8
Figure 1. Functional Block Diagram of the AX5045
An on-chip low power oscillator as well as Wake-on-radio
enable very low power standby applications. Figure 1 shows
the block diagram of the AX5045.
Digital IF
De-
channel
ADC
modulator
filter
Modulator
Chip configuration
POR
References
Low Power
Oscillator
Wake on Radio
640 Hz/10kHz
Voltage
Regulator
7
23,1
23
1
www.onsemi.com
APPLICATION NOTE
12
11
Communication Controller &
Serial Interface
Registers
19 20 21
14 15 16 17
Publication Order Number:
SPI
AND9902/D

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Summary of Contents for ON Semiconductor AX5045

  • Page 1: Overview

    Integrated +23 dBm High Power Amplifier APPLICATION NOTE OVERVIEW AX5045 is a true single chip low-power CMOS transceiver for narrow band applications. A fully integrated VCO support most carrier frequencies from 60 MHz to 1050 MHz. The on-chip transceiver consists of a fully integrated RF front-end with modulator, and demodulator.

  • Page 2: Table Of Contents

    AND9902/D Table of Contents Overview ....................FIFO Operation .
  • Page 3 (POR) block and can be performed manually via the register Microcontroller can directly run on that clock or use it to file. calibrate its internal oscillators. The AX5045 sends and receives data via the SPI port in frames. This standard operation mode is called frame mode. 25 24 AX5045...
  • Page 4 AND9902/D Pin Function Descriptions Table 1. PIN FUNCTION DESCRIPTION Symbol Pin(s) Type Description VDD_IO Power supply 3.0 V – 3.6 V VCHOKE Regulator Output to External PA choke inductors TX_P Differential TX antenna output TX_N Differential TX antenna output RX_P Differential RX antenna input RX_N Differential RX antenna input...
  • Page 5 AND9902/D SPI Register Access waveforms are compatible to most hardware SPI master Registers are accessed via a synchronous Serial Peripheral controllers, and can easily be generated in software. MISO Interface (SPI). Most Registers are 8 bits wide and accessed changes on the falling edge of CLK, while MOSI is latched using the waveforms as detailed in Figure 3.
  • Page 6 AND9902/D Table 2. SPI STATUS BITS (continued) SPI Bit Cell Status Register Bit WAKEUP INTERRUPT PENDING LPOSC INTERRUPT PENDING GPADC INTERRUPT PENDING undefined Note that bit cells 8−15 (S7…S0) are only available in two Address Space The address space has been allocated as follows. address byte SPI access formats.

  • Page 7: Fifo Operation

    AND9902/D FIFO OPERATION The AX5045 features a 256 Byte FIFO. The same FIFO receiver. Writing the ROLLBACK command to the is used for both reception and transmission. During transmit, FIFOSTAT register sets the write ahead pointer to the write only the write port is accessible by the microcontroller.
  • Page 8 AND9902/D Table 3. CHUNK PAYLOAD SIZE ENCODING (continued) Top Bits Chunk Payload Size Invalid Invalid Invalid Variable length payload; payload size is encoded in the following length byte the length byte is part of the header (and not included in length), everything after the length byte is included in the length The following table lists the chunk types and their FIFOIRQ Command encodings.
  • Page 9 AND9902/D FREQOFFS Command ANTRSSI2 Command Table 9. FREQOFFS COMMAND Table 10. ANTRSSI2 COMMAND FREQOFFS1 RSSI FREQOFFS0 BGNDNOISE The FREQOFFS command will only be generated by the The ANTRSSI2 command will be generated by the receiver at the end of a packet if bit ST FOFFS is set in receiver when it is idle if bit ST ANT RSSI is set in register register PKTSTOREFLAGS.
  • Page 10 AND9902/D ANTRSSI3 Command PKTSTOREFLAGS. If DIVENA is not set in register DIVERSITY, the ANTRSSI2 command is generated Table 15. ANTRSSI3 COMMAND instead. The encoding of the ANT0RSSI and ANT1RSSI fields are the same as that of the RSSI register. The BGNDNOISE field contains an estimate of the ANTORSSI2 background noise.
  • Page 11 AND9902/D ABORT is set if the packet has been aborted. An ABORT TXPWR Command sequence is a sequence of seven or more consecutive one bits Table 19. TXPWR COMMAND when HDLC [1] framing is used. Note that if ACCPT ABRT is not set in register PKTACCEPTFLAGS, then aborted packets are silently dropped.

  • Page 12: Programming The Chip

    This is controlled by the PWRMODE To enable the lowest possible application power register. Idd values are typical; for exact values, please refer consumption, the AX5045 allows to shut down its circuits to the AX5045 datasheet [2]. Table 20. PWRMODE REGISTER STATES...
  • Page 13 Inversion, differential, Manchester, scrambled, for recommendations see the description of the register ENCODING. The following table gives an overview of the trade-offs between the different modulations that AX5045 offers, they should be considered when making a choice. Table 22. TRADE-OFFS BETWEEN THE DIFFERENT MODULATION...
  • Page 14 This polynomial is used for Wireless M-Bus. Framing • CRC-32 (32bit): Figure 1 shows the block diagram of the AX5045. After the user writes a transmit packet into the FIFO, the Radio Controller sequences the transmitter start-up, and signals the (hexadecimal: 0x04C11DB7)
  • Page 15 AND9902/D transmission on the receiver side. The downside is that powers up the synthesizer and settles it (registers it now requires twice the amount of energy for the TMGTXBOOST and TMGTXSETTLE determine the transmission. Manchester is not recommended, except timing). The Preamble and the Packet(s) are then for compatibility with legacy systems.
  • Page 16 4−FSK mode (register FSKDMAX). encoder ensure enough transitions to acquire the bit timing. On the AX5045, these loops run in parallel. An AGC that In 4−FSK mode, send UNENCODED bytes 00010001. is significantly off however causes the received signal to fall...
  • Page 17 Antenna scanning is resumed WAKEUPFREQ register. after a packet is completed. After waking up, the AX5045 quickly settles the AGC and Actual packet data in the FIFO may be preceded and computes the channel RSSI. If it is below an absolute followed by meta-data.
  • Page 18 LO WORMULTIPKT is set in register PKTMISCFLAGS. frequency. During SYNTHBOOST, the synthesizer is In Wake-on-Radio mode, the AX5045 is completely operated higher loop...
  • Page 19 AND9902/D Figure 13. Receiver State Diagram Conditions are evaluated in priority order. The priority order to increase the precision of the wake-up frequency, number is given in parentheses at the beginning of arrow calibration logic allows the low power oscillator to be labels.
  • Page 20 AND9902/D Auxiliary DAC The AX5045 contains an auxiliary DAC. It can be used to PWRAMP output various receiver signals, such as RSSI or Frequency or ANTSEL Offset, or just a value under program control. The DAC signal can be output either on the PWRAMP or ANTSEL pad.

  • Page 21: Register Overview

    AND9902/D REGISTER OVERVIEW Table 23. CONTROL REGISTER MAP Addr Name Reset Description Revision & Interface Probing REVISION 01000110 SILICONREV(7:0) Silicon Revision SCRATCH 11000101 SCRATCH(7:0) Scratch Register Operating Mode PWRMODE 000–0000 XOEN REFEN PWRMODE(3:0) Power Mode Voltage Regulator POWSTAT –––––––– SSUM SREF SVREF SVANA...
  • Page 22 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description Status RADIOSTATE – ––––0000 – – – – RADIOSTATE(3:0) Radio Controller State –––––––– – – – – – – – XTAL Crystal XTALSTATUS Oscillator Status Pin Configuration PINSTATE –––––––– –...
  • Page 23 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description PLLCPIBOOST 11001000 PLLCPI PLL Charge Pump Current (Boosted) PLLRANGINGB1 00000001 STICK RNGE STICK VTUNE – VCOR LOCK START OFFR B(8) Autoranging LOCK OFFR PLLRANGINGB0 00000000 VCORB(7:0) Autoranging FREQB3 00111001 FREQB(31:24) Synthesizer Frequency...
  • Page 24 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description TIMERCLK ––––––10 – – – – – – CLKMUX(1:0) Internal Timer Clock Setting Time Stamp 00000000 RCTRLTIMESTAMP(23:16) Radio Controller RCTRLTIMESTAMP2 Timestamp Count 00000000 RCTRLTIMESTAMP(15:8) Radio Controller RCTRLTIMESTAMP1 Timestamp Count 00000000 RCTRLTIMESTAMP(7:0) Radio Controller...
  • Page 25 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description AFSKSPACE0 01000000 AFSKSPACE(7:0) AFSK Space (0) Frequency AFSKMARK1 ––––0000 – – – – AFSKMARK(11:8) AFSK Mark (1) Frequency 01110101 AFSKMARK(7:0) AFSK Mark (1) AFSKMARK0 Frequency AFSKCTRL –––00100 – – –...
  • Page 26 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description FREQDEV10 ––––0000 – – – – FREQDEV0(11:8) Receiver Frequency Deviation FREQDEV00 00100000 FREQDEV0(7:0) Receiver Frequency Deviation FOURFSK0 –––10110 – – – DEVDECAY0(3:0) Four FSK UPDAT Control BBOFFSRES0 10001000 RESINTB0(3:0) RESINTA0(3:0) Baseband Offset Compensation...
  • Page 27 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description FREQGAINC2 –––01101 – – – FREQGAINC2(4:0) Frequency Gain FREQGAIND2 01–01101 RFFRE ZIGZA – FREQGAIND2(4:0) Frequency Gain FREEZ FREEZ AMPLGAIN2 010–0110 AMPL AMPL AMPL – AMPLGAIN2(3:0) Amplitude Gain AVG2 AGC2 FREQDEV12 ––––0000 –...
  • Page 28 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description TXRATE2 00101000 TXRATE(23:16) Transmitter Bitrate TXRATE1 11110101 TXRATE(15:8) Transmitter Bitrate TXRATE0 11000011 TXRATE(7:0) Transmitter Bitrate 00000000 TXPWRCOEFFA(15:8) Transmitter TXPWRCOEFFA1 Predistortion Coefficient A TXPWRCOEFFA0 00000000 TXPWRCOEFFA(7:0) Transmitter Predistortion Coefficient A 00001111 TXPWRCOEFFB(15:8) Transmitter...
  • Page 29 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description Baseband BBTUNE 0––01001 COAR – – BBTUNE(3:0) Baseband SE BW TUNE Tuning BBOFFSCAP –111–111 – CAP INT B(2:0) – CAP INT A(2:0) Baseband Offset Compensation Capacitors ADCCLK –0111100 – CLKFREQ(4:0) CLKMUX(1:0) SAR ADC Clock...
  • Page 30 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description MATCH0APAT1 00000000 MATCH0APAT(15:8) Pattern Match Unit 0a, Pattern MATCH0APAT0 00000000 MATCH0APAT(7:0) Pattern Match Unit 0a, Pattern MATCH0ALEN 0––00000 MATC – – MATCH0ALEN(4:0) Pattern Match Unit 0a, Pattern Length MATCH0AMIN –––00000 –...
  • Page 31 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description TMGRXRSSI 00000000 TMGRXRSSIE(2:0) TMGRXRSSIM(4:0) Receiver RSSI Settling Time 00000000 TMGRXPREAMBLE1E(2:0) TMGRXPREAMBLE1M(4:0) Receiver TMGRXPREAMBLE1 Preamble 1 Timeout 00000000 TMGRXPREAMBLE2E(2:0) TMGRXPREAMBLE2M(4:0) Receiver TMGRXPREAMBLE2 Preamble 2 Timeout 00000000 TMGRXPREAMBLE3E(2:0) TMGRXPREAMBLE3M(4:0) Receiver TMGRXPREAMBLE3 Preamble 3 Timeout 00000000...
  • Page 32 AND9902/D Table 23. CONTROL REGISTER MAP (continued) Addr Name Reset Description LPOSCFREQ0 0000–––– LPOSCFREQ(1:−2) – – – – Low Power Oscillator Calibration Frequency LPOSCPER1 –––––––– LPOSCPER(15:8) Low Power Oscillator Calibration Period LPOSCPER0 –––––––– LPOSCPER(7:0) Low Power Oscillator Calibration Period DACVALUE1 ––––0000 –...

  • Page 33: Register Details

    Description SCRATCH 11000101 Scratch Register The SCRATCH register does not affect the function of the chip in any way. It is intended for the Microcontroller to test communication to the AX5045. Operating Mode PWRMODE Table 26. PWRMODE Name Bits Reset...
  • Page 34 AND9902/D Power Management POWSTAT Table 28. POWSTAT Name Bits Reset Description SVIO − IO Voltage Large Enough (not Brownout) SBEVMODEM − Modem Domain Voltage Brownout Error (Inverted; 0 = Brownout, 1 = Power OK) SBEVANA − Analog Domain Voltage Brownout Error (Inverted;...
  • Page 35 AND9902/D Interrupt Control IRQMASK1, IRQMASK0 Table 31. IRQMASK1, IRQMASK0 Name Bits Reset Description IRQMFIFONOTEMPTY FIFO not empty interrupt enable IRQMFIFONOTFULL FIFO not full interrupt enable FIFO count > threshold interrupt enable IRQMFIFOTHRCNT FIFO free > threshold interrupt enable IRQMFIFOTHRFREE IRQMFIFOERROR FIFO error interrupt enable IRQMPLLUNLOCK PLL status (lock lost / V...
  • Page 36 AND9902/D IRQINVERSION1, IRQINVERSION0 Table 33. IRQINVERSION1, IRQINVERSION0 Name Bits Reset Description IRQINVFIFONOTEMPTY FIFO not empty interrupt inversion IRQINVFIFONOTFULL FIFO not full interrupt inversion FIFO count > threshold interrupt inversion IRQINVFIFOTHRCNT FIFO free > threshold interrupt inversion IRQINVFIFOTHRFREE IRQINVFIFOERROR FIFO error interrupt inversion IRQINVPLLUNLOCK PLL status (lock lost / V off range) interrupt inversion (depends...
  • Page 37 AND9902/D IRQREQUEST1, IRQREQUEST0 Table 34. IRQREQUEST1, IRQREQUEST0 Name Bits Reset Description IRQRQFIFONOTEMPTY − FIFO not empty interrupt pending IRQRQFIFONOTFULL − FIFO not full interrupt pending FIFO count > threshold interrupt pending IRQRFIFOTHRCNT − FIFO free > threshold interrupt pending IRQRFIFOTHRFREE −...
  • Page 38 AND9902/D ENCODING1, ENCODING0 Table 38. ENCODING1, ENCODING0 Name Bits Reset Description INV(0) Invert the 2 bit of DiBit symbols in 4−FSK mode; else ignore this config bit INV(1) Invert data if set to 1; in 4−FSK mode only the 1 bit of DiBit symbols is inverted DIFF Differential Encode/Decode data if set to 1...
  • Page 39 ENCODING1 is set to 1). It is recommended to NOTE: The wireless M-Bus definition of “Manchester” use syncwords containing an even number of is inverse to the definition used by the AX5045. bits and to ensure DiBit alignment during AX5045 defines “Manchester” as the...
  • Page 40 AND9902/D CRCCFG Table 42. CRCCFG Name Bits Reset Description CRCNOINV Do not invert CRC bits if set to 1 CRCMODE See Table 43: CRCMODE Bit Values Table 43. CRCMODE BIT VALUES NOTE: By default, CRC bits get inverted by the framing Bits Meaning logic.
  • Page 41 AND9902/D FECSYNC Table 46. FECSYNC Name Bits Reset Description FECSYNC 01100010 Interleaver Synchronization Threshold FECSTATUS Table 47. FECSTATUS Name Bits Reset Description MAXMETRIC − Metric increment of the survivor path FEC INV − Inverted Synchronization Sequence received Status RADIOSTATE Table 48. RADIOSTATE Name Bits Reset...
  • Page 42 AND9902/D PINFUNCSYSCLK Table 52. PINFUNCSYSCLK Name Bits Reset Description PFSYSCLK 00010 See Table 53: PFSYSCLK Bit Values PUSYSCLK SYSCLK weak Pullup enable Table 53. PFSYSCLK BIT VALUES Bits Meaning 0000 Idle 00000 SYSCLK Output ‘0’ 00001 SYSCLK Output ‘1’ 00010 SYSCLK Output ‘Z’...
  • Page 43 AND9902/D Table 55. PFDCLK BIT VALUES (continued) DCLK Output Modem Data Clock Input; use when inputting/outputting framing data on DATA DCLK Output Modem Data Clock Output; use when observing modem data on DATA DCLK Output Modem Data Clock Output; use when inputting/outputting framing data on DATA, and you do not want to generate a clock yourself DCLK Output DSPmode frame sync...
  • Page 44 AND9902/D PINFUNCANTSEL Table 60. PINFUNCANTSEL Name Bits Reset Description PFANTSEL See Table 61: PFANTSEL Bit Values PIANTSEL ANTSEL inversion PUANTSEL ANTSEL weak Pullup enable Table 61. PFANTSEL BIT VALUES Bits Meaning ANTSEL Output ‘0’ ANTSEL Output ‘1’ ANTSEL Output ‘Z’ ANTSEL Output Baseband Tune Clock ANTSEL Output External TCXO Enable ANTSEL Output DAC...
  • Page 45 AND9902/D FIFO Registers FIFOSTAT Table 65. FIFOSTAT Name Bits Reset Description FIFO EMPTY FIFO is empty if 1 FIFO FULL FIFO is full if 1 FIFO UNDER FIFO underrun occurred since last read of FIFOSTAT when 1 FIFO OVER FIFO overrun occurred since last read of FIFOSTAT when 1 1 if the FIFO count is >...
  • Page 46 AND9902/D FIFOTHRESH Table 70. FIFOTHRESH Name Bits Reset Description FIFOTHRESH 00000000 FIFO Threshold Synthesizer PLLLOOP, PLLLOOPBOOST The PLLLOOP and PLLLOOPBOOST select PLL Loop mode. All fields in this register are separate, except for Filter configuration for both normal mode and boosted FREQSEL, which is common to both registers.
  • Page 47 AND9902/D PLLVCODIV Table 74. PLLVCODIV Name Bits Reset Description REFDIV See Table 75: REFDIV Bit Value RFDIV RF divider Bits Ratio 1050 unused unused unused Settings of REFDIV & RFDIV are fully taken in Table 75. REFDIV BIT VALUES account by the internal circuitry (i.e. there is no need to Bits Meaning adjust FREQA/B or other registers).
  • Page 48 AND9902/D FREQA3, FREQA2, FREQA1, FREQA0 Table 77. FREQA3, FREQA2, FREQA1, FREQA0 Name Bits Reset Description FREQA 31:0 0x3934CCCD CARRIER FREQ + Frequency; XTAL It is not recommended to use an RF frequency that is an It is strongly recommended to always set bit 0 to avoid integer multiple of the reference frequency, due to stray RF spectral tones.
  • Page 49 AND9902/D TRKAMPL1, TRKAMPL0 Table 84. TRKAMPL1, TRKAMPL0 Name Bits Reset Description TRKAMPL 15:0 − Current amplitude tracking value TRKPHASE1, TRKPHASE0 Table 85. TRKPHASE1, TRKPHASE0 Name Bits Reset Description TRKPHASE 11:0 − Current phase tracking value TRKRFFREQ2, TRKRFFREQ1, TRKRFFREQ0 Table 86. TRKRFFREQ2, TRKRFFREQ1, TRKRFFREQ0 Name Bits Reset...
  • Page 50 AND9902/D Tracking Register Resets Writes to TRKAMPL1, TRKAMPL0, TRKPHASE1, TRKPHASE0, TRKDATARATE2, TRKDATARATE1, TRKDATARATE0 cause the following action: Table 90. TRACKING REGISTER RESET Name Bits Reset Description DTRKRESET − Writing 1 clears the Datarate Tracking Register ATRKRESET − Writing 1 clears the Amplitude Tracking Register PTRKRESET −...
  • Page 51 AND9902/D RCTRLTIMESTAMP2, RCTRLTIMESTAMP1, RCTRLTIMESTAMP0 Table 93. RCTRLTIMESTAMP2, RCTRLTIMESTAMP1, RCTRLTIMESTAMP0 Name Bits Reset Description RCTRLTIMESTAMP 23:0 0x000000 Timestamp Count To commit the value in the RCTRLTIMESTAMP register While writing the RCTRLTIMESTAMP register via SPI as a valid transmit timestamp, the bit TIMETX ENA in burst mode, the internal logic is pulling the corresponding register RCTRLTIMETXENA has to be set to 1.
  • Page 52 AND9902/D Receiver Parameters IFFREQ1, IFFREQ0 Table 99. IFFREQ1, IFFREQ0 Name Bits Reset Description IFFREQ 15:0 0x1327 IFFREQ + IF Frequency; XTAL Please use the AX_RadioLab software to calculate the optimum IF frequency for given physical layer parameters. DECIMATION Table 100. DECIMATION1, DECIMATION0 Name Bits Reset...
  • Page 53 AND9902/D This register sets the maximum frequency offset the Bandwidth, at the expense of slightly reducing the built-in Automatic Frequency Correction (AFC) should Sensitivity. handle. Set it to the maximum frequency offset between At the cost of extended preamble length it is also possible Transmitter and Receiver.
  • Page 54 AND9902/D AFSKCTRL Table 108. AFSKCTRL Name Bits Reset Description AFSKSHIFT 00100 AFSK Detector Bandwidth; BITRATE DECIMATION 3dB corner frequency of the AFSK detector filter is: ) 2k * 2 arccos k 2(k * 1) DECIMATION AFSKSHIFT with AMPLFILTER Table 109. AMPLFILTER Name Bits Reset...
  • Page 55 AND9902/D FREQUENCYLEAK Table 113. FREQUENCYLEAK Name Bits Reset Description FREQUENCYLEAK 0000 Leakiness of the Baseband Frequency Recovery Loop (0000 = off) PHHALFACC Half bit phase accumulation; accumulate phase (as FSK decision variable) only over the center half bit; this makes decision more robust against shaping, at a slight loss in sensitivity RXPARAMSETS Table 114.
  • Page 56 AND9902/D LNABIAS Table 119. LNABIAS Name Bits Reset Description LNABIAS 0000 LNABIAS is thermometer coded and sets the bias for the LNA. For proper operation, these bits need to be written to 0011. This value is a stable setting across operating conditions. System sensitivity can be degraded if not set accordingly.
  • Page 57 AND9902/D AGCREDUCE0, AGCREDUCE1, AGCREDUCE2, AGCREDUCE3 Table 123. AGCREDUCE0, AGCREDUCE1, AGCREDUCE2, AGCREDUCE3 Name Bits Reset Description AGCMAXDA0 When the digital AGC attenuation exceeds its maximum value, it is reset to the value given in AGCMAXDAx, and the analog AGC AGCMAXDA1 gain is recomputed accordingly. This value is given in 3 dB AGCMAXDA2 steps.
  • Page 58 AND9902/D DRGAIN0, DRGAIN1, DRGAIN2, DRGAIN3 Table 126. DRGAIN0, DRGAIN1, DRGAIN2, DRGAIN3 Name Bits Reset Description DRGAIN0E 0010 Gain of the datarate recovery loop; this is the exponent DRGAIN1E 0001 DRGAIN2E 0000 DRGAIN3E 0000 Gain of the datarate recovery loop; this is the mantissa DRGAIN0M 1111 DRGAIN1M...
  • Page 59 AND9902/D FREQGAINA0, FREQGAINA1, FREQGAINA2, FREQGAINA3 Table 129. FREQGAINA0, FREQGAINA1, FREQGAINA2, FREQGAINA3 Name Bits Reset Description Gain of the baseband frequency recovery loop; the frequency FREQGAINA0 1111 error is measured with the phase detector FREQGAINA1 1111 FREQGAINA2 1111 FREQGAINA3 1111 If set to 1, only update the frequency offset recovery loops if the FREQAMPLGATE0 amplitude of the signal is larger than half the maximum (or larger FREQAMPLGATE1...
  • Page 60 AND9902/D FREQGAINC0, FREQGAINC1, FREQGAINC2, FREQGAINC3 Table 131. FREQGAINC0, FREQGAINC1, FREQGAINC2, FREQGAINC3 Name Bits Reset Description Gain of the RF frequency recovery loop; the frequency error is FREQGAINC0 01010 measured with the phase detector FREQGAINC1 01011 FREQGAINC2 01101 FREQGAINC3 01101 Set FREQGAINC0 = 31 and FREQGAIND0 = 31 to completely disable the RF frequency recovery loop, setting its output to zero.
  • Page 61 AND9902/D AMPLGAIN0, AMPLGAIN1, AMPLGAIN2, AMPLGAIN3 Table 133. AMPLGAIN0, AMPLGAIN1, AMPLGAIN2, AMPLGAIN3 Name Bits Reset Description AMPLGAIN0 0110 Gain of the amplitude recovery loop AMPLGAIN1 0110 AMPLGAIN2 0110 AMPLGAIN3 0110 if 1, the amplitude tracking register is also updated between two AMPLHS0 samples AMPLHS1...
  • Page 62 AND9902/D DCLK PWRAMP DATA Figure 22. Wiremode Timing Diagram Wiremode is also available in 4−FSK mode, see Figure 22. The two bits that encode one symbol are serialized on the DATA pin. The PWRAMP pin can be used as a Figure 21.
  • Page 63 AND9902/D Table 138. AMOUNT OF LEAKAGE (continued) 0111 1000 1001 1010 1011 1419 1100 2839 1101 5678 1110 11356 1111 22713 BBOFFSRES0, BBOFFSRES1, BBOFFSRES2, BBOFFSRES3 Table 139. BBOFFSRES0, BBOFFSRES1, BBOFFSRES2, BBOFFSRES3 Name Bits Reset Description RESINTA0 1000 Baseband Gain Block A Offset Compensation Resistors RESINTA1 RESINTA2 RESINTA3...
  • Page 64 AND9902/D FSKDEV2, FSKDEV1, FSKDEV0 Table 142. FSKDEV2, FSKDEV1, FSKDEV0 Name Bits Reset Description FSKDEV 23:0 0x000A3D (G)FSK Frequency DEVIATION Deviation; FSKDEV + XTAL Note that f is actually half the deviation. The In AM and FM mode, the register has a different DEV IATION mark frequency is definition.
  • Page 65 AND9902/D If BROWN GATE is set, the transmitter is disabled Table 146. AMPLSHAPE BIT VALUES whenever one (or more) of the SSVIO, SSBEVMODEM or Bits Meaning SSBEVANA bits of the POWSTICKYSTAT register is zero. Unshaped In order for this to work, the user must read the Raised Cosine POWSTICKYSTAT after setting the PWRMODE register for transmission.
  • Page 66 AND9902/D TXPWRCOEFFD1, TXPWRCOEFFD0 Table 152. TXPWRCOEFFD1, TXPWRCOEFFD0 Name Bits Reset Description TXPWRCOEFFD 15:0 0x0000 Transmit Predistortion, TXPWRCOEFFD + a See TXPWRCOEFFB for an explanation. TXPWRCOEFFE1, TXPWRCOEFFE0 Table 153. TXPWRCOEFFE1, TXPWRCOEFFE0 Name Bits Reset Description TXPWRCOEFFE 15:0 0x0000 Transmit Predistortion, TXPWRCOEFFE + a See TXPWRCOEFFB for an explanation.
  • Page 67 AND9902/D PLL Parameters PLLVCOI Table 156. PLLVCOI Name Bits Reset Description VCOI This field sets the bias current for the VCO. There is a trade−off between current and phase noise. PLLLOCKDET Table 157. PLLLOCKDET Name Bits Reset Description LOCKDETDLY See Table 158: LOCKDETDLY Bit Values LOCKDETDLYM 0 = Automatic Lock Delay (determined by the currently active frequency register);...
  • Page 68 AND9902/D PLLRNGCFG Table 159. PLLRNGCFG Name Bits Reset Description PLLRNGCLK See Table 160: PLLRNGCLK Bit Values PLLRNGMODE Bits Meaning Sequential, using V window comparator tune Sequential, using center frequency measurement Successive Approximation, using V window tune comparator Successive Approximation, using center frequency measurement Test mode for V window comparator...
  • Page 69 AND9902/D PLLSTATMASK This register sets the PLL events for which an interrupt is triggered if bit IRQMPLLSTAT is set in register IRQMASK0. Table 162. PLLSTATMASK Name Bits Reset Description PLLVTUNEOFF VCO V out−of−range interrupt mask tune PLLUNLOCK PLL lock lost interrupt mask When PLLVTUNEOFF is enabled, the VCO V tune comparator ADC is always−on.
  • Page 70 AND9902/D XTALAMPL Table 165. XTALAMPL Name Bits Reset Description XTALREGVC Crystal Oscillator Critical Amplitude Bits Critical Amplitude 180 mV 195 mV 230 mV … … 460 mV XTALREGON Crystal Oscillator Amplitude Regulator Enable Baseband BBTUNE Table 166. BBTUNE Name Bits Reset Description BBTUNE...
  • Page 71 AND9902/D ADCMISC Table 169. ADCMISC Name Bits Reset Description CALSAMPLES Number of samples to average the ADC calweights Bits Meaning 4 Samples 8 Samples 16 Samples Invalid SKIP CALIB Skip calibration and scaling during ADC startup REF BUF Higher BW for reference buffer Packet Format PKTADDRCFG Table 170.
  • Page 72 AND9902/D PKTLENOFFSET1, PKTLENOFFSET0 Table 173. PKTLENOFFSET1, PKTLENOFFSET0 Name Bits Reset Description LEN OFFSET 12:0 0x0000 Packet Length Offset The receiver adds LEN OFFSET to the length byte. The Mode specific Framing 0x03 value of (length byte + LEN OFFSET) counts every byte in With PKTLENPOS = 0x00, PKTLENBITS = 0x00 and the packet after the synchronization pattern, up to and PKTLENOFFSET = 0x003, the receiver will correctly...
  • Page 73 AND9902/D PKTADDRMASK4, PKTADDRMASK3, PKTADDRMASK2, PKTADDRMASK1, PKTADDRMASK0 Table 178. PKTADDRMASK4, PKTADDRMASK3, PKTADDRMASK2, PKTADDRMASK1, PKTADDRMASK0 Name Bits Reset Description ADDRMASK 39:0 0x00000000 Packet Address Mask The Packet Address Mask is the same for both PKTADDRA and PKTADDRB. Pattern Match MATCH0PAT3, MATCH0PAT2, MATCH0PAT1, MATCH0PAT0 Table 179.
  • Page 74 AND9902/D MATCH0BPAT3, MATCH0BPAT2, MATCH0BPAT1, MATCH0BPAT0 Table 183. MATCH0BPAT3, MATCH0BPAT2, MATCH0BPAT1, MATCH0BPAT0 Name Bits Reset Description MATCH0BPAT 31:0 0x00000000 Pattern for Match Unit 0b. LSB is received first; patterns of length less than 32 must be MSB aligned One can optionally choose to allow matching on a 2nd MATCH0BMIN and MATCH0BMAX), whereas the option syncword: MATCH0BPAT.
  • Page 75 AND9902/D MATCH1MAX Table 190. MATCH1MAX Name Bits Reset Description MATCH1MAX 1111 A match is signalled if the received bitstream matches the pattern in more than MATCH1MAX positions. Packet Controller TMGTXBOOST Table 191. TMGTXBOOST Name Bits Reset Description TMGTXBOOSTM 10010 Transmit PLL Boost Time Mantissa TMGTXBOOSTE Transmit PLL Boost Time Exponent The Transmit PLL Boost Time is TMGTXBOOSTM ⋅...
  • Page 76 AND9902/D TMGRXOFFSACQ0 Table 195. TMGRXOFFSACQ0 Name Bits Reset Description TMGRXOFFSACQ0M 10110 Baseband DC Offset Acquisition Time Mantissa TMGRXOFFSACQ0E Baseband DC Offset Acquisition Time Exponent The first stage Baseband DC Offset Acquisition Time is [TIMER Period] = period of the internal timer as set by TMGRXOFFSACQ0M ⋅...
  • Page 77 AND9902/D TMGRXRSSI Table 200. TMGRXRSSI Name Bits Reset Description TMGRXRSSIM 00000 Receiver RSSI Settling Time Mantissa TMGRXRSSIE Receiver RSSI Settling Time Exponent The Receiver RSSI Settling Time is TMGRXRSSIM ⋅ [TIMER Period] is determined by bit RXRSSI CLK in TMGRXRSSIE .
  • Page 78 AND9902/D BGNDRSSIGAIN Table 206. BGNDRSSIGAIN Name Bits Reset Description BGNDRSSIGAIN 0000 Background RSSI Averaging Time Constant The background RSSI estimate BGNDRSSI is updated The update is performed as follows: BGNDRSSI = BGNDRSSI + (RSSI − BGNDRSSI) ⋅ 2 −BGNDRSSIGAIN whenever the antenna RSSI is measured (after antenna selection, if diversity is enabled), see the Radio Controller RXANTRSSI state.
  • Page 79 Accept Packets that are too long ACCPT LRGP Accept Packets that span multiple FIFO chunks General Purpose ADC AX5045 can also be used as a General Purpose ADC indicate completion of a conversion. Alternatively, bit 7 (GPADC). To chip GPADC mode, (BUSY) of register GPADCCTRL can be polled.
  • Page 80 AND9902/D GPADCVALUE1, GPADCVALUE0 Table 214. GPADC13VALUE1, GPADC13VALUE0 Name Bits Reset Description GPADCVALUE 13:0 − GPADC Value (unsigned; 12 bits + 2 sub−bits) Reading this register clears the GPADC Interrupt. Low Power Oscillator Calibration LPOSCCONFIG Table 215. LPOSCCONFIG Name Bits Reset Description LPOSC ENA Enable the Low Power Oscillator.
  • Page 81 AND9902/D LPOSCREF1, LPOSCREF0 Table 219. LPOSCREF1, LPOSCREF0 Name Bits Reset Description LPOSCREF 15:0 0x61A8 LP Oscillator Reference Frequency Divider; set to 640 Hz LPOSCFREQ1, LPOSCFREQ0 Table 220. LPOSCFREQ1, LPOSCFREQ0 Name Bits Reset Description LPOSCFREQ 9:-2 0x000 LP Oscillator Frequency Tune Value; in LPOSCPER1, LPOSCPER0 Table 221.

  • Page 82: References

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