F3B: Sdti Block Diagram (Aj-Yac930G: Option) - Panasonic DVCPRO50 Service Manual

F3B: SDTI BLOCK DIAGRAM (AJ-YAC930G: OPTION)

IC3201<3>
J3200
EQ &
1 6
CLK GEN
SDTI INPUT
BLACK
28 29
S OUT2
YELLOW
1
1
S OUT1
ORANGE
P3002 P3000
13B 13B REF_CLK27_SDTI
P3000
OUT FRM
10A
(REF FRM)
P3000
9C REF CF
P3002 P3000
19A 21C DIF_CLK18
P3002 P3000
19C 22B REC_DIF_FRP
20A 22C REC_DIF_SSP
21C 24B PB_DIF_FRP
22A 24C PB_DIF_SSP
P3000
18
12B ISP TDO
11A ISP TDI
11B ISP TMS
11C ISP TCK
P3400
2 TDO
3 TDI
6 TMS
8 TCK
IC3204<3>
32 SDO(DATA)
SERIAL
TO
PARALLEL
17,28
31 SDO(DATA)
10
19-25
SCO(270MCLK) 7
1
16
X
SCO(270MCLK) 8
10
IC3301<4>
P2S_DATA
25
(10Bit X 27MHz)
PARALLEL
SDTO[0-9]
1-10
TO
24 SERIAL
11
IC3103<2>
BUFF 16 P2S CLK
2 14 SDT CLK1
12
SDT CLK2
OUT FRM
REF CF
IC3104<2>
16 DIF CLK(18MHz)
2
BUFF
IC3400<5>
IC3403<5>
PLD
2
28 TDO
4 16 13
TDI
14
6 25
TMS
8 12 32
TCK
IC3404<5>
38
SDRAM
120
37,38,
S2P_DATA
40,41
(10bit x 27MHz)
44-46
S2P_D[0-9]
49-51
S2P CLK(27MHz) 31
SDRAM
IF
27MHz 18MHz
Delay
57-63
10 65-67
134
131
X2 PLL
165
166
BUS_IF/SYS_IF/SDRAM_CTRL
SDTI_FORMATTER/EDH
27
14
15
9
13
82
132,133
2,7,31
DATA & CLK
IC3105<2>
IC3402<5>
REC_BD[0-3]
(4bit x 18MHz) 6-9
4
17-20
11-14
BUFF
163 CF 15
162 F
16
160 H
17
PB_DIF_BD[0-3]
4 (4bit x 18MHz)
2,5-7
IC3100,
3101<1/2>
187-8
190-198
AV_ADRS:11bit
BUFF
IC3102<2>
BUFF
18-11 2-9
200-207
AV_DATA:8bit
IC3101<2/2>
BUFF
77 RD_L 14 6
181 WR_L 13 7
184 CS_L 12 8
29 RST_L 11 9
167
168
170
P3000 P3002
4
REC DIF BD 23A-C 20B-C,
[0-3] 24A 21A-B
P3000
P3002
DIF CF 17A 23C
DIF FRM 22A 19B
DIF HS 17B 24A
P3000 P3002
PB DIF BD 25A-C 22B-C,
[0-3] 26A 23A-B
P3000
5C
AV ADRS[0-10]
2B
P3000
9B
AV DATA[0-7]
7A
P3000
AV_IORD_L 6A
AV_IOWR_L 6B
AV_CS_DIF_L 2A
AV_RST_L 6C
P3000
SYS_FRP 10B
P3000
SYS_SSP 14B
P3000
SYS_FEND 10C