F5: V_Out Block Diagram - Panasonic DVCPRO50 Service Manual

F5: V_OUT BLOCK DIAGRAM

IC3015<2>
P3002 P3002
BUFFER
8 14
29A 29A PB_CLK27
17 3
25A 7A EE_CLK27
29B 26C
PB_YC[0-7]
31A 29B
50 49 1-4,24-27 IC3082<5>
8
10-13,
58-65
15-18
1-9
89 WE_F1 22
6
88 WRST_F1
5 FIFO1
87 RE_F1 8,9
20
86 RRST_F1 19
11-19
1-4,24-27 IC3080<5>
10-13,
15-18
22
20
5
FIFO2
TBC_IC 8,9
6
19
1-4,24-27 IC3083<5>
68-75 10-13,
15-18
91 WE_F2 22
20
54
WRST_F2 5
FIFO1
56 RE_F2 8,9
6
55 RRST_F2
19
41
IC3081<5>
21 1-4,24-27
10-13,
15-18
22
IC3070<4>
20
5
76-79, FIFO2
8,9
82-84
6
19
TBC_CTRL_Signal
TBC_R_CLK 7
IC3051<3>
Delay
16
TBC_W_CLK
2
FIFO_W_CLK 14
5 11
FIFO_R_CLK
RST_W
WCK
RST_R
1-4,
P3000 P3001 6 5 19
24-28
8
19A 19C
REC_YC[0-7]
FIFO
21B 22A 4-7,15-18
8
20
IC3017<2>
RCK
P3002 P3002 IC3016<2>
6 14
ENC_CTRL E_CF
25B 6A EE_CF
5 15
25C 6B EE_FRM
4 16
26A 6C EE_HD
3 17
28B 28B PB_FRM
2 18
ENC_CTRL
28C 28C PB_FRM2
ENC_CTRL
PB_FRM
BUFFER
PB_FRM2
P3001 P3001
11
9
18A 18C INCOM_CF
ENC_CTRL
ENC_CTRL
E_HD
IN_CF
IC3011
P1 P3001 <2>
2-9
22C 22C
AV_ADRS[0-10] IN_BUFF
26A 26A
7-9
IC3012<2>
P1 P3001 BUFF
4 16
26C 26C AV_IOWR_L
2 18
27A 27A AV_RST_L
5 15
26B 26B AV_IORD_L
3 17
22B 22B AV_CS_VOUT_L
OE
P1 P3001 19 1
DIR
27B 27B
AV_DATA[0-7] IN_BUFF
29C 29C
2-9
P3010
IP3010<2>
IC3013<2>
2 TDO
13
3 TDI
TDI
25
6 TMS
32
8 TCK
28
IC3010<2>
TDO
P600 P3001
4 16
ROM for
3 6A ISP_TDI
TBC_CTRL FPGA
6 14
6 6B ISP_TMS
IP3018<2>
8 12
8 6C ISP_TCK 13
TDI
2 7A ISP_TDO 25
32
P101 P3001 BUFF
TDO
7C 7C CONF_INFO
ROM for ENC_CTRL_FPGA
IC3606<13>
RSY_A
3
(H SYNC)
Comparator
IC3600<13> 11
P100 P3001
28D 7B ISP_SEL5 VR3600
1
CF_ADJ_M
24D 14A REF_IN SYNC_SEPA
3
INT_135
IC3052<3> IC3090<6>
27 80-88 91
[0-9]
CK
200-207
16-27 Y 10
Interpolation
1,2, [0-9]
Y/C 10
92-100 42-52 C
12-20 SEP
149-158
8
91 65,66,
2-11
73,74
Y
8 8
30-38 8
13.5MHz CLK
EDGE
54-61
40-49
COMB
62-70 C
TBC_CTRL
FPGA
(PLD)
8
[2-9]
Y
8
165-173
C
[2-9]
Y/C_SEP
157-164
82,83,132,133
DATA & CLK
177-179
EVR DATA & CLK
I2C
DEC
84,85
TBC
74,
CTRL
87-89
IC3903<16>
BUFFER
16
18
51
17
14
73
9
50 12
FLFO
77
CTRL
TBC_CLK
188
190
187
ENC_CTRL
E_FRM
PROCESS_BUS / AV_BUS
DATA & CLK
TP3701
2,
7,
IC3702,
31
IC3705<14>
SCPC(SC Phase control)
S/H
68 67 IC3802<15>
TP3802
CF_TP2
SYNC
GENE
2, TP3803
7,
CF_TP1
31
2
69
REF_BURST
GATE
IC3607<13>
63
TP3600
REF
64
R_HS
CF
6
DET
9 1 65
13
REF
5
CF
ADJ
VR3601
IC3608<13> CF_ADJ_S CF_ADJ for 625 mode (AJ-SD955A only)
FRM_FRZ_H
IC3154<8>
FLD_FRZ_H
EEPROM
1-8
IC3100<7>
IC3153<8>
31 174 173 84,70-74
109-119
69
143,147
2-11 ENC_CTRL_FPGA (PLD)
PROCESS
CTRL
Process
Amp
10
Y+C
SYNC
Blanking
54-66 ADD
54-63
123
127-141
65-68
INTERPOLATION
SYS_H
69 CONTROL
FIFO
32
IN_CF
33
E_CF REF
GEN
34
E_FRM
35
E_HD
40
PB_FRM
SLOPE
41
PB_FRM2
191-207
AV_BUS PIO
82,83,132,133
106-108
EVR ENC_CTL
DATA GEN
GEN
PROC_CLK
ENC_CLK
DAC CLK
27
RSY_A 2
H_RESET 22
BFP 45 WFM SEL
12 18 48 47 19 20 87-90
1-3
IC3202<9>
NENT_SYNC_DC
SITE_SYNC_DC
VCO
D/A
SITE_SETUP
SC_ADJ
For 625 mode (AJ-SD955A only)
WFM_ENV
X3700<14> IC3709<14>
3
4fsc 7
Comparator
VCO
VC3700
X3701<14> REF 4fsc
3
4fsc 7
Comparator
VCO
IC3710<14>
VC3701
FREQ_ADJ
47,54
98
SCH ON H
4
11
WFM_CTL
114
IC3704<14>
5
ERR
IC3707 5
Comparator
4
<14>
TP3804 TP3806
WND
CF FRM
VR3700 SYS_SC
VR3701 SYS SC for 625 mode (AJ-SD955A only)
2-9
10
8,9
4
3
2
142 8
7
141
121 CHR_CLK 9
138 OUT_FRM
152
TC_FRM 6
151
SYNC_L
150
NENT_SYNC_DC
10 Q3200,3205<9> IC3208<9>
94-104 4
5
Fix 7
ENCODER
DC_Adj
1-10
Delay
&
18
DA IC3204<9>
FL3202<9>
Q3202,3206 3
Y_OUT
55
IC3309<10>
COMPONENT
Y LEVEL ADJ 5
7
I2C DATA 1,3,4
Y LEVEL ADJ
for SCH ADJ
IC3206<9>
1
3
91-93 LPF
PB_OUT
54
7,8
5 FL3200<9>
Delay
39-41
adj
IC3305
<10>
7 5
IC3306<10>
PB LEVEL ADJ
FL3201<9>
IC3207<9>
7,8 1
Delay
LPF
adj
PR_OUT
51
5
7
5
IC3308
PR LEVEL ADJ
Fix
Delay Q3402,3407<11>
C3412
YCY_OUT
47
Fix
SETUP
ADD Gain
IC3403
R3440-45
Q3409,3412<11> <11>
NTSC ONLY
SETUP_ON_H
IC3416<11>
COMPOSITE Y
7,8
YCC_OUT
46
5 Delay 18
adj FL3401<11>
Composite C Timing DATA
IC3201<9>
BUFF
IC3508<12>
5
CHR_DATA_H BUFF
WFM_RF IC3506<12>
7
1,2
4
7
1
3
2
5
4
2
1
4
7
5
3
IC3507<12>
IC3706<14> X3702<14>
PHASE SYS
3
ERROR PLL
7 1
27M CLK (SYNCRONIZED to H SYNC of REF)
27M CLK
IC3900<16> P3001 P3000
15B 14B
10
SDI YC [0-9]
18B 17B
BUFF
11-18
IC3901<16>
11,12
P3002 P3002
BUFF
16
REF-CF 27B 27B
17
REF_FRM
27C 27C
18
REF_HD 28A 28A
IC3902<16>
P3002 P2
12
CHR_VSYNC_L 19A 14B
BUFF
P3002 P2
13
CHR_HSYNC_L 19B 13C
P3002 P2
11
CHR_CLK 18C 14A
15
OUT_FRM 12C 13B
P3002 P2
14
TC_FRM 12B 13A
Q3300,
IC3304<10>
3304<10>
3 P3001 P100
6
LPF
9 Y_OUT 11A 26B
AMP BUFF
2
COMPONENT
Y FREQ ADJ DATA
IC3310<10>
7 5
PB LEVEL ADJ DATA
3
P3001 P100
6
2 AMP BUFF PB_OUT 12A 26C
Q3301,
3306<10>
PB FREQ ADJ DATA
5
7
PB FREQUENCY ADJ
IC3311<10>
Q3302,3308
IC3307<10>
3
3
P3001 P100
6
13A 26D
2 AMP BUFF PR_OUT
PR FREQUENCY ADJ DATA
IC3312<10>
COMPOSITE Y
IC3402,Q3406,
Y FREQ ADJ DATA
DC_Adj
3408<11>
FL3400<11> IC3408
<11>
9
LPF
6
18 3 AMP
1
4 2
5
7
3
7
IC3409<11>
1
Y Frequerey ADJ
2
5
IC3407<11>
IC3406<11>
Y LEVEL ADJ
LEVEL ADJ DATA
7
IC3415<11>
3
9
LPF
6
AMP
5 2
7
IC3414<11>
COMPOSITE C
PB LEVEL ADJ
LEVEL ADJ DATA
Q3508,3512 P3001 P100
VIDEO_OUT1 8C 25B
Q3509,3514
VIDEO_OUT2 9B 25C
VIDEO_OUT3 10A 25D
BUFF
Q3510,
3516
P3002 P2
CHR_DATA_H
CHR_DATA_H 20A 15B
CHR_GATE_H
CHR_GATE_H 19C 15A
WFM_TC
WFM_TC 4B 3C
P3002 P5901
WFM_ENV
WFM_ENV 3C 23B
WFM_RF
WFM_RF 3A 23C
P3002 P700
WFM_CTL
WFM_CTL 5A 26B
IC3904<16>
P3001 P3001
18
REF_CLK27_SDI 15A 14A
P3002 P3002
11 16
REF_CLK27_RP 27A 27A
BUFF
P3002 P4001
14
REF_CLK27_AP 24A 22C
P3002 P3002
12
REF_CLK27_SDTI 13B