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Silicon Laboratories Si4330 Manual

Ism receiver
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Si4330 ISM R
Features
Frequency Range = 240–960 MHz
Sensitivity = –118 dBm
Low Power Consumption
18.5 mA receive

Data Rate = 1 to 128 kbps
Power Supply = 1.8 to 3.6 V
Ultra low power shutdown mode
Digital RSSI
Wake-up timer
Auto-frequency calibration (AFC)
Clear channel assessment
Programmable RX BW 2.6–620 kHz
Programmable packet handler
Programmable GPIOs
Applications
Remote control
Home security & alarm
Telemetry
Personal data logging
Toy control
Tire pressure monitoring
Wireless PC peripherals
Description
Silicon Laboratories' Si4330 highly integrated, single chip wireless ISM receiver is
part of the EZRadioPRO™ family. The EZRadioPRO family includes a complete
line of transmitters, receivers, and transceivers allowing the RF system designer
to choose the optimal wireless part for their application.
The Si4330 offers advanced radio features including continuous frequency
coverage from 240–960 MHzThe Si4330's high level of integration offers reduced
BOM cost while simplifying the overall system design. The extremely low receive
sensitivity (–118 dBm) ensures extended range and improved link performance.
Built-in antenna diversity and support for frequency hopping can be used to
further extend range and enhance performance.
Additional system features such as an automatic wake-up timer, low battery
detector, 64 byte RX FIFO, automatic packet handling, and preamble detection
reduce overall current consumption and allow the use of lower-cost system
MCUs. An integrated temperature sensor, general purpose ADC, power-on-reset
(POR), and GPIOs further reduce overall system cost and size.
The Si4330's digital receive architecture features a high-performance ADC and
DSP based modem which performs demodulation, filtering, and packet handling
for increased flexibility and performance. This digital architecture simplifies
system design while allowing for the use of lower-end MCUs.
Preliminary Rev 0.2 2/09
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
ECEIVER
Embedded antenna diversity
algorithm
Configurable packet structure
Preamble detector
RX 64 byte FIFO
Low battery detector
Temperature sensor and 8-bit ADC
–40 to +85 °C temperature range
Integrated voltage regulators
Frequency hopping capability
On-chip crystal tuning
20-Pin QFN package
FSK, GFSK, and OOK modulation
Low BOM
Power-on-reset (POR)
Remote meter reading
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
Tag readers
Copyright © 2009 by Silicon Laboratories
Si4330
Ordering Information:
See page 139.
Pin Assignments
Si4330
20
19 18 17
16
VDD_RF
1
15
NC
2
14
RXp
3
13
RXn
4
12
VR_IF
5
11
6
7
8
9
10
Metal
Paddle
Patents pending
SCLK
SDI
SDO
VDD_DIG
NC
Si4330

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Summary of Contents for Silicon Laboratories Si4330

  • Page 1  Metal Paddle Description Silicon Laboratories’ Si4330 highly integrated, single chip wireless ISM receiver is part of the EZRadioPRO™ family. The EZRadioPRO family includes a complete line of transmitters, receivers, and transceivers allowing the RF system designer Patents pending to choose the optimal wireless part for their application.
  • Page 2 Si4330 Functional Block Diagram VDD_RF RC 32K OSC RF LDO PLL LDO VCO LDO 30M XTAL Temp Sensor 8Bit Digital Logic SCLK ANTDIV SPI, & Controller VDD_DIG Digital Modem AGC Control Low Power Digital LDO Digital LDO Mixers IF LDO...

  • Page 3: Table Of Contents

    Si4330 ABLE O F ONTENTS Section Page 1. Electrical Specifications ...........7 1.1.
  • Page 4 13. Pin Descriptions: Si4330 ........
  • Page 5 Si4330 I S T OF IGURES Figure 1. RX Application Example.................... 14 Figure 2. SPI Timing........................16 Figure 3. SPI Timing—READ Mode ..................17 Figure 4. SPI Timing—Burst Write Mode .................. 17 Figure 5. SPI Timing—Burst Read Mode .................. 17 Figure 6. State Machine Diagram....................18 Figure 7.
  • Page 6 Si4330 I S T OF ABLES Table 1. DC Characteristics .......................7 Table 2. Synthesizer AC Electrical Characteristics ..............8 Table 3. Receiver AC Electrical Characteristics ...............9 Table 4. Auxiliary Block Specifications ...................10 Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ........11 Table 6.

  • Page 7: Electrical Specifications

    Si4330 1. Electrical Specifications Table 1. DC Characteristics Parameter Symbol Conditions Max Units Supply Voltage Range Power Saving Modes — RC Oscillator, Main Digital Regulator, Shutdown and Low Power Digital Regulator OFF — — Low Power Digital Regulator ON (Register values retained)

  • Page 8: Table 2. Synthesizer Ac Electrical Characteristics

    Si4330 Table 2. Synthesizer AC Electrical Characteristics Parameter Symbol Conditions Units Synthesizer Frequency Low Band — SYNTH-LB Range High Band — SYNTH-HB Synthesizer Frequency Low Band — 156.25 — RES-LB Resolution High Band — 312.5 — RES-HB Reference Frequency —...

  • Page 9: Table 3. Receiver Ac Electrical Characteristics

    Si4330 Table 3. Receiver AC Electrical Characteristics Parameter Symbol Conditions Units RX Frequency Low Band — SYNTH-LB Range High Band — SYNTH-HB RX Sensitivity (BER < 0.1%) — –118 — RX_2 (2 kbps, GFSK, BT = 0.5, f = 5 kHz) (BER <...

  • Page 10: Table 4. Auxiliary Block Specifications

    Si4330 Table 4. Auxiliary Block Specifications Parameter Symbol Conditions Units Temperature Sensor When calibrated using temp — — °C Accuracy sensor offset register Temperature Sensor — — mV/°C Sensitivity Low Battery Detector — — Resolution Low Battery Detector — —...

  • Page 11: Table 5. Digital Io Specifications (Sdo, Sdi, Sclk, Nsel, And Nirq)

    Si4330 Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) Parameter Symbol Conditions Units Rise Time 0.1 x V to 0.9 x V = 5 pF — — RISE Fall Time 0.9 x V to 0.1 x V = 5 pF —...

  • Page 12: Table 7. Absolute Maximum Ratings

    Si4330 Table 7. Absolute Maximum Ratings Parameter Value Unit to GND –0.3, +3.6 Voltage on Digital Control Inputs –0.3, V + 0.3 Voltage on Analog Inputs –0.3, V + 0.3 RX Input Power C Operating Ambient Temperature Range T –40 to +85 Thermal Impedance ...

  • Page 13: Definition Of Test Conditions

    External reference signal (XIN) = 1.0 V at 30 MHz, centered around 0.8 VDC Production test schematic (unless noted otherwise) All RF input and output levels referred to the pins of the Si4330 (not the RF module) Extreme Test Conditions: = –40 to +85 °C = +1.8 to +3.6 VDC...

  • Page 14: Functional Description

    8–10 dB, resulting in substantial range increases depending on the environmental conditions. The Si4330 is designed to work with a microcontroller, crystal, and a few passives to create a very low cost system. Voltage regulators are integrated on-chip which allow for a wide range of operating supply voltage conditions from +1.8 to +3.6 V.

  • Page 15: Operating Modes

    Table 8 summarizes the modes of operation of the Si4330. In general, any given mode of operation may be classified as an Active mode or a Power Saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode.

  • Page 16: Controller Interface

    Select high period To read back data from the Si4330, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R/W = 0. The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register.

  • Page 17: Figure 3. Spi Timing-Read Mode

    Figure 4 and burst read in Figure 3. As long as nSEL is held low, input data will be latched into the Si4330 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 5.

  • Page 18: Operating Mode Control

    Si4330 3.2. Operating Mode Control There are three primary states in the Si4330 radio state machine: SHUTDOWN, IDLE, and RX (see Figure 6). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs.
  • Page 19 Si4330 3.2.1. Shutdown State The shutdown state is the lowest current consumption state of the device with nominally less than 10 nA of current consumption. The shutdown state may be entered by driving the SDN pin (Pin 20) high. The SDN pin should be held low in all states except the SHUTDOWN state.
  • Page 20 Si4330 1. Enable the Main Digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is “0”, default value is “1”).

  • Page 21: Interrupts

    Si4330 3.3. Interrupts The Si4330 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur.

  • Page 22: System Timing

    Si4330 3.5. System Timing The system timing for RX mode is shown in Figure 7. If a small range of frequencies is being used and the temperature range is fairly constant a calibration may only be needed at the initial power up of the device. The relevant system timing registers are shown below.

  • Page 23: Frequency Control

    3.6.1. Frequency Programming In order to receive an RF signal, the desired channel frequency, fcarrier, must be programmed into the Si4330. Note that this frequency is the center frequency of the desired channel and not an LO frequency. The carrier...

  • Page 24: Table 11. Frequency Band Selection

    Si4330 Table 11. Frequency Band Selection fb[4:0] Value Frequency Band hbsel=0 hbsel=1 240–249.9 MHz 480–499.9 MHz 250–259.9 MHz 500–519.9 MHz 260–269.9 MHz 520–539.9 MHz 270–279.9 MHz 540–559.9 MHz 280–289.9 MHz 560–579.9 MHz 290–299.9 MHz 580–599.9 MHz 300–309.9 MHz 600–619.9 MHz 310–319.9 MHz...
  • Page 25 3.6.2. Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the Si4330, it is often easier to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register.

  • Page 26: Figure 8. Frequency Deviation

    Si4330 carrier Time Figure 8. Frequency Deviation The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency;...

  • Page 27: Figure 9. Sensitivity At 1% Per Vs. Carrier Frequency Offset

    Si4330 3.6.5. Frequency Offset Adjustment When the AFC is disabled the frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The frequency offset adjustment and the AFC both are implemented by shifting the Synthesizer Local Oscillator frequency.
  • Page 28 Si4330 The AFC function shares registers 73h and 74h with the Frequency Offset setting. If AFC is enabled (D6 in “Register 1Dh. AFC Loop Gearshift Override,” on page 92), the Frequency Offset shows the results of the AFC algorithm for the current receive slot. When selecting the preamble length, the length needs to be long enough to settle the AFC.

  • Page 29: Modulation Options

    Si4330 4. Modulation Options 4.1. FIFO Mode In FIFO mode, the integrated FIFO is used to receive the data. The FIFO is accessed via "Register 7Fh. FIFO Access" with burst read capability. The FIFO may be configured specific to the application packet size, etc. (see "6.

  • Page 30: Internal Functional Blocks

    Si4330 5. Internal Functional Blocks This section provides an overview some of the key blocks of the internal radio architecture. 5.1. RX LNA The input frequency range for the LNA is 240–960 MHz. The LNA provides gain with a noise figure low enough to suppress the noise of the following stages.

  • Page 31: Synthesizer

    Si4330 The Invalid Preamble Detector issues an interrupt when no valid preamble signal is found. After the receiver is enabled, the Invalid Preamble Detector output is ignored for 16 Tb (Where Tb is the time of a bit duration) to allow the receiver to settle.

  • Page 32: Crystal Oscillator

    5.7. Crystal Oscillator The Si4330 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 µs when a suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components.

  • Page 33: Data Handling And Packet Handler

    Si4330 6. Data Handling and Packet Handler 6.1. RX FIFO A 64 byte FIFO is integrated into the chip for RX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to access the FIFO. A burst read, as described in "3.1. Serial Peripheral Interface (SPI)" on page 16, from address 7Fh will read data from the RX FIFO.

  • Page 34: Packet Configuration

    Si4330 6.2. Packet Configuration When using the FIFO, automatic packet handling may be enabled for the RX mode. "Register 30h. Data Access Control" through “Register 39h. Synchronization Word 0,” on page 107 and “Register 3Fh. Check Header 3,” on page 108 through “Register 4Bh. Received Packet Length,” on page 112 control the configuration, status, and decoded RX packet data for Packet Handling.

  • Page 35: Figure 14. Multiple Packets In Rx Packet Handler

    Si4330 RX FIFO Contents: Transmission: rx_multi_pk_en = 0 rx_multi_pk_en = 1 Register eader(s) txhdlen = 0 txhdlen > 0 Data fixpklen fixpklen Register ength Data Data FIFO Data Data Data Data Data Figure 14. Multiple Packets in RX Packet Handler...

  • Page 36: Table 13. Packet Handler Registers

    Si4330 Table 13. Packet Handler Registers Function/Description POR Def. Data Access Control enpacrx lsbfrst crcdonly *Reserved Reserved encrc crc[1] crc[0] EzMAC status Reserved rxcrc1 pksrch pkrx pkvalid crcerror Reserved Reserved — Header Control 1 bcen[3] enbcast[2] enbcast[1] enbcast[0] hdch[3] hdch[2]...

  • Page 37: Data Whitening, Manchester Encoding, And Crc

    Figure 16. Operation of Data Whitening, Manchester Encoding, and CRC 6.5. Preamble Detector The Si4330 has integrated automatic preamble detection. The preamble length is configurable from 1–256 bytes using the prealen[7:0] field in "Register 33h. Header Control 2" and "Register 34h. Preamble Length", as described in “6.2.

  • Page 38: Invalid Preamble Detector

    Si4330 Table 14. Minimum Receiver Settling Time Mode Approximate Recommended preamble Recommended preamble receiver settling time length with 8-bit length with 20-bit detection threshold detection threshold (G)FSK AFC Disabled 1 byte 20 bits 32 bits (G)FSK AFC Enabled 2 byte...

  • Page 39: Rx Modem Configuration

    Si4330 7. RX Modem Configuration 7.1. Modem Settings for FSK and GFSK The modem performs channel selection and demodulation in the digital domain. The channel filter bandwidth is configurable from 620 to 2.6 kHz. The data-rate, modulation index, and bandwidth are set via registers 1C–25. The modulation index is equal to 2 times the peak deviation divided by the data rate (Rb).
  • Page 40 Si4330 7.1.1. Advanced FSK and GFSK Settings In nearly all cases, the information in Table 15, “RX Modem Configurations for FSK and GFSK,” on page 39 can be used to determine the required FSK and GFSK modem parameters. The section includes a more detailed discussion of the various modem parameters to allow for experienced designers to further configure the modem performance.

  • Page 41: Table 16. Filter Bandwidth Parameters

    Si4330 Table 16. Filter Bandwidth Parameters ndec_exp dwn3_bypass filset BW [kHz] ndec_exp dwn3_bypass filset [kHz] 1C-[6:4] 1C-[7] 1C-[3:0] 1C-[6:4] 1C-[7] 1C-[3:0] 41.7 45.2 47.9 56.2 64.1 69.2 75.2 83.2 90.0 95.3 112.1 127.9 137.9 142.8 167.8 10.6 181.1 11.5 191.5 12.1...

  • Page 42: Modem Settings For Ook

    7.2. Modem Settings for OOK The Si4330 is configured for OOK mode by setting the modtyp[1:0] field to OOK in "Register 71h. Modulation Mode Control 2". In OOK mode, the following parameters can be configured: data rate, manchester coding, channel filter bandwidth, and the clock recovery oversampling rate.

  • Page 43: Table 18. Ndec[2:0] Settings

    Si4330 Table 18. ndec[2:0] Settings Rb(1+ enmanch) [kbps] ndec[2:0] The clock recovery oversampling rate is set via rxosr[10:0] in "Register 20h. Clock Recovery Oversampling Rate" and "Register 21h. Clock Recovery Offset 2". ndec_exp and dwn3_bypass together with the receive data rate (Rb) are used to calculate rxosr: ...

  • Page 44: Table 19. Rx Modem Configuration For Ook With Manchester Disabled

    Si4330 Table 19. RX Modem Configuration for OOK with Manchester Disabled RX Modem Setting Examples for OOK (Manchester Disabled) Appl Parameters Register Values RX BW dwn3_bypass ndec_exp[2:0] filset[3:0] rxosr[10:0] ncoff[19:0] crgain[10:0] [kbps] [kHz] 20,21h 21,22,23h 24,25h 09D49 09D49 0346E 0346E...

  • Page 45: Auxiliary Functions

    8. Auxiliary Functions 8.1. Smart Reset The Si4330 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable reset signal in any circumstances.

  • Page 46: Microcontroller Clock

    If the microcontroller clock option is being used there may be the need of a System Clock for the microcontroller while the Si4330 is in SLEEP mode. Since the Crystal Oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock.

  • Page 47: General Purpose Adc

    Si4330 8.3. General Purpose ADC An 8-bit SAR ADC is integrated onto the chip for general purpose use, as well as for digitizing the temperature sensor reading. “Register 0Fh. ADC Configuration,” on page 86 must be configured depending on the use of the GP ADC before use.

  • Page 48: Figure 19. Adc Differential Input Example-Bridge Sensor

    Si4330 8.3.1. ADC Differential Input Mode—Bridge Sensor Example The differential input mode of ADC8 is designed to directly interface any bridge-type sensor, which is demonstrated in the figure below. As seen in the figure the use of the ADC in this configuration will utilize two GPIO pins. The supply source of the bridge and chip should be the same to eliminate the measuring error caused by battery discharging.

  • Page 49: Figure 20. Adc Differential Input Offset For Sensor Offset Coarse Compensation

    Si4330 The differential offset can be coarse compensated by the adcoffs[3:0] bits found in "Register 11h. ADC Value". Fine compensation should be done by the microcontroller software. The main reason for the offset compensation is to shift the negative offset voltage of the bridge sensor to the positive differential voltage range. This is essential as the differential input mode is unipolar.

  • Page 50: Temperature Sensor

    Si4330 8.4. Temperature Sensor An analog temperature sensor is integrated into the chip. The temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is selected on the analog test bus.

  • Page 51: Figure 21. Temperature Ranges Using Adc8

    Si4330 Temperature Measurement with ADC8 Sensor Range 0 Sensor Range 1 Sensor Range 2 Sensor Range 3 Temperature [Celsius] Figure 21. Temperature Ranges using ADC8 Preliminary Rev 0.2...

  • Page 52: Low Battery Detector

    Si4330 8.5. Low Battery Detector A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold". When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller.

  • Page 53: Wake-Up Timer

    Si4330 8.6. Wake-Up Timer The chip contains an integrated wake-up timer which periodically wakes the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode.

  • Page 54: Figure 22. Wut Interrupt And Wut Operation

    Si4330 Interrupt Enable enwut=1 (Reg 06h) WUT Period GPIOX=00001 nIRQ SPI Interrupt Read Chip State Sleep Ready Sleep Ready Sleep Ready Sleep Current Consumption 600n 600n 600n Interrupt Enable enwut =0 (Reg 06h) WUT Period GPIOX=00001 nIRQ SPI Interrupt Read...

  • Page 55: Low Duty Cycle Mode

    Si4330 8.7. Low Duty Cycle Mode The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available. The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT period.

  • Page 56: Gpio Configuration

    Si4330 8.8. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, Antenna Diversity Switch control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low.

  • Page 57: Antenna-Diversity

    Si4330 8.9. Antenna-Diversity To mitigate the problem of frequency-selective fading due to multi-path propagation, some radio systems use a scheme known as Antenna Diversity. In this scheme, two antennas are used. Each time the radio enters RX mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the preamble portion of the packet.

  • Page 58: Rssi And Clear Channel Assessment

    Si4330 8.10. RSSI and Clear Channel Assessment The RSSI (Received Signal Strength Indicator) signal is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI value can be read from an 8-bit register with 0.5 dB resolution per bit. Figure 24 demonstrates the relationship between input power level and RSSI value.

  • Page 59: Reference Design

    Si4330 9. Reference Design Preliminary Rev 0.2...

  • Page 60: Table 24. Receiver Bill Of Materials

    Si4330 Table 24. Receiver Bill of Materials Part Value Device Package Description 33 pF C-USC0603K 0603 Capacitor, Murata GRM18 sereies 100 pF C-USC0603K 0603 Capacitor, Murata GRM18 sereies 100 nF C-USC0603K 0603 Capacitor C-USC0603K 0603 Capacitor C-USC0603K 0603 Capacitor, Murata GRM18 sereies...

  • Page 61: Figure 26. Receiver-Top

    Si4330 Figure 26. Receiver—Top Figure 27. Receiver—Top Silkscreen Preliminary Rev 0.2...

  • Page 62: Figure 28. Receiver-Bottom

    Si4330 Figure 28. Receiver—Bottom Note: The reference design shown above is the that of the standard testcard that may be ordered directly from Silicon Labs. Within this reference design is a EEPROM called the EBID (Evaluation Board IDentification). The EBID is used by other Silicon Labs development tools and is not required on customer designs.

  • Page 63: Measurement Results

    Si4330 10. Measurement Results Sensitivity vs. Data Rate Measured at RX SMA Connector Input -100 dBm -102 dBm -104 dBm -106 dBm -108 dBm -110 dBm -112 dBm -114 dBm -116 dBm -118 dBm -120 dBm 1 kbps 10 kbps...

  • Page 64: Figure 30. Receiver Selectivity

    Si4330 Adjacent Channel Selectivity at 50 kbps Measured at RX SMA Connector Input 10 dB AGC Enabled 0 dB -10 dB -20 dB -30 dB -40 dB -50 dB -60 dB -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00...

  • Page 65: Figure 31. Synthesizer Settling Time For 1 Mhz Jump Settled Within 10 Khz

    Si4330 Si4330 Figure 31. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz Figure 32. Synthesizer Phase Noise (VCOCURR = 11) Preliminary Rev 0.2...

  • Page 66: Application Notes

    Si4330 11. Application Notes 11.1. Crystal Selection The recommended crystal parameters are given in Table 25. Table 25. Recommended Crystal Parameters Frequency Frequency Accuracy 30 MHz 60 Ω 12 pF 5 pF ±20 ppm The internal XTAL oscillator will work over a range for the parameters of ESR, CL, C0, and ppm accuracy. Extreme values may affect the XTAL start-up and sensitivity of the link.

  • Page 67: Matching Network Design

    Si4330 11.3. Matching Network Design 11.3.1. RX LNA Matching Figure 33. RX LNA Matching Table 26. RX Matching for Different Bands Freq Band 915 MHz 6.8 pF 11.0 nH 3.3 pF 868 MHz 6.8 pF 11.0 nH 3.9 pF 433 MHz 10.0 pF...

  • Page 68: Reference Material

    Si4330 12. Reference Material 12.1. Complete Register Table and Descriptions Table 27. Register Descriptions Function/Desc Data Default Device Type dt[4] dt[3] dt[2] dt[1] dt[0] 01000 Device Version vc[4] vc[3] vc[2] vc[1] vc[0] Device Status ffovfl ffunfl rxffem headerr reserved reserved...
  • Page 69 Si4330 Table 27. Register Descriptions (Continued) Function/Desc Data Default Check Header 1 chhd[15] chhd[14] chhd[13] chhd[12] chhd[11] chhd[10] chhd[9] chhd[8] Check Header 0 chhd[7] chhd[6] chhd[5] chhd[4] chhd[3] chhd[2] chhd[1] chhd[0] Header Enable 3 hden[31] hden[30] hden[29] hden[28] hden[27] hden[26]...
  • Page 70 Si4330 Register 00h. Device Type Code (DT) Reserved dt[4:0] Name Type Reset value = 00001000 Name Function Reserved Reserved. dt[4:0] Device Type Code. EZRadioPRO: 01000. Register 01h. Version Code (VC) Reserved vc[4:0] Name Type Reset value = xxxxxxxx Name Function Reserved Reserved.
  • Page 71 Si4330 Register 02h. Device Status ffovfl ffunfl rxffem headerr Reserved Reserved cps[1:0] Name Type Reset value = xxxxxxxx Name Function ffovfl RX FIFO Overflow Status. ffunfl RX FIFO Underflow Status. rxffem RX FIFO Empty Status. headerr Header Error Status. Indicates if the received packet has a header check error.
  • Page 72 Si4330 Register 03h. Interrupt/Status 1 ifferr Reserved Reserved irxffafull iext Reserved ipkvalid icrerror Name Type Reset value = xxxxxxxx Name Function ifferr FIFO Underflow/Overflow Error. When set to 1 the RX FIFO has overflowed or underflowed. Reserved Reserved. irxffafull RX FIFO Almost Full. When set to 1 the RX FIFO has met its almost full threshold and needs to be read by the microcontroller.

  • Page 73: Table 28. Interrupt Or Status 1 Bit Set/Clear Description

    Si4330 Table 28. Interrupt or Status 1 Bit Set/Clear Description Status Set/Clear Conditions Name ifferr Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset. Reserved Reserved. irxffafull Set when the number of bytes in the RX FIFO is greater than the Almost Full threshold.
  • Page 74 Si4330 Register 04h. Interrupt/Status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor Name Type Reset value = xxxxxxxx Name Function iswdet Sync Word Detected. When a sync word is detected this bit will be set to 1. ipreaval Valid Preamble Detected.

  • Page 75: Table 30. Interrupt Or Status 2 Bit Set/Clear Description

    Si4330 Table 30. Interrupt or Status 2 Bit Set/Clear Description Status Set/Clear Conditions Name iswdet Goes high once the Sync Word is detected. Goes low once we are done receiving the cur- rent packet. ipreaval Goes high once the preamble is detected. Goes low once the sync is detected or the RX wait for the sync times-out.
  • Page 76 Si4330 Register 05h. Interrupt Enable 1 enfferr Reserved Reserved enrxffafull enext Reserved enpkvalid encrcerror Name Type Reset value = 00000000 Name Function enfferr Enable FIFO Underflow/Overflow. When set to 1 the FIFO Underflow/Overflow interrupt will be enabled. Reserved Reserved. enrxffafull Enable RX FIFO Almost Full.
  • Page 77 Si4330 Register 06h. Interrupt Enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor Name Type Reset value = 00000011 Name Function enswdet Enable Sync Word Detected. When mpreadet =1 the Preamble Detected Interrupt will be enabled. enpreaval Enable Valid Preamble Detected.
  • Page 78 Si4330 Register 07h. Operating Mode and Function Control 1 swres enlbd enwt x32ksel Reserved rxon pllon xton Name Type Reset value = 00000001 Name Function swres Software Register Reset Bit. This bit may be used to reset all registers simultaneously to a DEFAULT state, without the need for sequentially writing to each individual register.
  • Page 79 Si4330 Register 08h. Operating Mode and Function Control 2 antdiv[2:0] rxmpk Reserved enldm ffclrrx Reserved Name Type Reset value = 00000000 Name Function antdiv[2:0] Enable Antenna Diversity. The GPIO must be configured for Antenna Diversity for the algorithm to work properly.
  • Page 80 Si4330 Register 09h. 30 MHz Crystal Oscillator Load Capacitance xtalshft xlc[6:0] Name Type Reset value = 01111111 Name Function xtalshft Additional capacitance to course shift the frequency if xlc[6:0] is not sufficient. Not binary with xlc[6:0]. xlc[6:0] Tuning Capacitance for the 30 MHz XTAL.
  • Page 81 Si4330 Register 0Ah. Microcontroller Output Clock Reserved clkt[1:0] enlfc mclk[2:0] Name Type Reset value = xx000110 Name Function Reserved Reserved. clkt[1:0] Clock Tail. If enlfc = 0 then it can be useful to provide a few extra cycles for the microcontroller to complete its operation.
  • Page 82 Si4330 Register 0Bh. GPIO Configuration 0 gpiodrv0[1:0] pup0 gpio0[4:0] Name Type Reset value = 00000000 Name Function gpiodrv0[1:0] GPIO Driving Capability Setting. pup0 Pullup Resistor Enable on GPIO0. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input.
  • Page 83 Si4330 Register 0Ch. GPIO Configuration 1 gpiodrv1[1:0] pup1 gpio1[4:0] Name Type Reset value = 00000000 Name Function gpiodrv1[1:0] GPIO Driving Capability Setting. pup1 Pullup Resistor Enable on GPIO1. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input.
  • Page 84 Si4330 Register 0Dh. GPIO Configuration 2 gpiodrv2[1:0] pup2 gpio2[4:0] Name Type Reset value = 00000000 Name Function gpiodrv2[1:0] GPIO Driving Capability Setting. pup2 Pullup Resistor Enable on GPIO2. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input.
  • Page 85 Si4330 Register 0Eh. I/O Port Configuration Reserved extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 Name Type Reset value = 00000000 Name Function Reserved Reserved. extitst[2] External Interrupt Status. If the GPIO2 is programmed to be external interrupt sources then the status can be read here.
  • Page 86 Si4330 Register 0Fh. ADC Configuration adcstart/ adcsel[2:0] adcref[1:0] adcgain[1:0] Name adcdone Type Reset value = 00000000 Name Function adcstart/adc- ADC Measurement Start Bit. done Reading this bit gives 1 if the ADC measurement cycle has been finished. adcsel[2:0] ADC Input Source Selection.
  • Page 87 Si4330 Register 10h. ADC Sensor Amplifier Offset Reserved adcoffs[3:0] Name Type Reset value = xxxx0000 Name Function Reserved Reserved. adcoffs[3:0] ADC Sensor Amplifier Offset*. *Note: The offset can be calculated as Offset = adcoffs[2:0] x VDD / 1000; MSB = adcoffs[3] = Sign bit.
  • Page 88 Si4330 Register 12h. Temperature Sensor Calibration tsrange[1:0] entsoffs entstrim tstrim[3:0] Name Type Reset value = 00100000 Name Function tsrange[1:0] Temperature Sensor Range Selection. (FS range is 0..1024 mV) –40 C .. 64 C (full operating range), with 0.5 C resolution (1 LSB in the 8-bit ADC) –40 C ..
  • Page 89 Si4330 Note: If a new configuration is needed (e.g., for the WUT or the LDC), proper functionality is required. The function must first be disabled, then the settings changed, then enabled back on. Register 14h. Wake-Up Timer Period 1 Reserved...
  • Page 90 Si4330 Register 17h. Wake-Up Timer Value 1 wtm[15:8] Name Type Reset value = xxxxxxxx Name Function wtm[15:8] Wake Up Timer Current Mantissa (M) Value*. *Note: The period of the wake-up timer can be calculated as T = (4 x M x 2 ) / 32.768 ms.
  • Page 91 Si4330 Register 1Ah. Low Battery Detector Threshold Reserved lbdt[4:0] Name Type Reset value = xxx10100 Name Function Reserved Reserved. lbdt[4:0] Low Battery Detector Threshold. This threshold is compared to Battery Voltage Level. If the Battery Voltage is less than the threshold the Low Battery Interrupt is set.
  • Page 92 Si4330 Register 1Ch. IF Filter Bandwidth dwn3_bypass ndec_exp[2:0] filset[3:0] Name Type Reset value = 00000001 Name Function dwn3_bypass Bypass Decimator by 3 (if set). ndec_exp[2:0] IF Filter Decimation Rates. filset[3:0] IF Filter Coefficient Sets. Defaults are for Rb = 40 kbps and Fd = 20 kHz so Bw = 80 kHz.
  • Page 93 Si4330 Register 1Eh. AFC Timing Control Reserved shwait[2:0] anwait[2:0] Name Type Reset value = xx001010 Name Function Reserved Reserved. shwait[2:0] Short Wait Periods after AFC Correction. Used before preamble is detected. Short wait = (RegValue + 1) x 2T If set to 0 then no AFC correction will occur before preamble detect, i.e.
  • Page 94 Si4330 Register 1Fh. Clock Recovery Gearshift Override Reserved rxready crfast[2:0] crslow[2:0] Name Type Reset value = 00000011 Name Function Reserved Reserved. rxready Improves Receiver Noise Immunity when in Direct Mode. It is recommended to set this bit after preamble is detected. When in FIFO mode this bit should be set to “0”...
  • Page 95 Si4330 Register 20h. Clock Recovery Oversampling Rate rxosr[7:0] Name Type Reset value = 01100100 Name Function rxosr[7:0] Oversampling Rate. 3 LSBs are the fraction, default = 0110 0100 = 12.5 clock cycles per data bit ndec_exp The oversampling rate can be calculated as rxosr = 500 kHz/(2 x RX_DR).
  • Page 96 Si4330 Register 21h. Clock Recovery Offset 2 rxosr[10:8] stallctrl ncoff[19:16] Name Type Reset value = 00000001 Name Function rxosr[10:8] Oversampling Rate. Upper bits. stallctrl Used for BCR Purposes. ncoff[19:16] NCO Offset. See formula above. The offset can be calculated as follows: ...
  • Page 97 Si4330 Register 23h. Clock Recovery Offset 0 ncoff[7:0] Name Type Reset value = 10101110 Name Function ncoff[7:0] NCO Offset. See formula above Register 24h. Clock Recovery Timing Loop Gain 1 Reserved crgain[10:8] Name Type Reset value = 00000010 Name Function Reserved Reserved.
  • Page 98 Si4330 Register 26h. Received Signal Strength Indicator rssi[7:0] Name Type Reset value = 00000000 Name Function rssi[7:0] Received Signal Strength Indicator Value. Register 27h. RSSI Threshold for Clear Channel Indicator rssith[7:0] Name Type Reset value = 00011110 Name Function rssith[7:0] RSSI Threshold.
  • Page 99 Si4330 Register 29h. Antenna Diversity 2 adrssi2[7:0] Name Type Reset value = 00000000 Name Function adrssi2[7:0] Measured RSSI Value on Antenna 2. Register 2Ah. AFC Limiter Afclim[7:0] Name Type Reset value = 00101010 Name Function Afclim[7:0] AFC Limiter. AFC limiter value.
  • Page 100 Si4330 Register 2Ch. OOK Counter Value 1 afc_corr[1:0] ookfrzen peakdeten madeten ookcnt[10] ookcnt[9] ookcnt[8] Name Type Reset value = 00101100 Name Function afc_corr[1:0] AFC Correction Values. AFC loop correction values [1:0] (LSBs). Values are updated once, after sync word is found during receiving.
  • Page 101 Si4330 Register 2Eh. Slicer Peak Holder Reserved attack[2:0] decay[3:0] Name Type Reset value = 00101110 Name Function Reserved Reserved. attack[2:0] Attack. decay[3:0] Decay. Register 30h. Data Access Control enpacrx lsbfrst crcdonly Reserved Reserved encrc crc[1:0] Name Type Reset value = 10001101...
  • Page 102 Si4330 ® Register 31h. EZMAC Status Reserved rxcrc1 pksrch pkrx pkvalid crcerror Reserved Name Type Reset value = 00000000 Name Function Reserved Reserved. rxcrc1 If high, it indicates the last CRC received is all one’s. May indicated Transmitter underflow in case of CRC error.
  • Page 103 Si4330 Register 32h. Header Control 1 bcen[3:0] hdch[3:0] Name Type Reset value = 00001100 Name Function bcen[3:0] Broadcast Address (FFh) Check Enable. If it is enabled together with Header Byte Check then the header check is OK if the incoming header byte equals with the appropriate check byte or FFh). One hot encoding.
  • Page 104 Si4330 Register 33h. Header Control 2 Reserved hdlen[2:0] fixpklen synclen[1:0] prealen[8] Name Type Reset value = 00100010 Name Function Reserved Reserved. hdlen[2:0] Header Length. Length of header used if packet handler is enabled for RX (enpacrx). Headers are received in descending order.
  • Page 105 Si4330 Register 34h. Preamble Length prealen[7:0] Name Type Reset value = 00001000 Name Function prealen[7:0] Preamble Length. The value in the prealen[8:0] register corresponds to the number of nibbles (4 bits) in the packet. For example prealen[8:0] = ‘000001000’ corresponds to a preamble length of 32 bits (8 x 4bits) or 4 bytes.
  • Page 106 Si4330 Register 36h. Synchronization Word 3 sync[31:24] Name Type Reset value = 00101101 Name Function sync[31:24] Synchronization Word 3. byte of the synchronization word. Register 37h. Synchronization Word 2 sync[23:16] Name Type Reset value = 11010100 Name Function sync[23:16] Synchronization Word 2.
  • Page 107 Si4330 Register 39h. Synchronization Word 0 sync[7:0] Name Type Reset value = 00000000 Name Function sync[7:0] Synchronization Word 0. byte of the synchronization word. Register 3Eh. Packet Length pklen[7:0] Name Type Reset value = 00000000 Name Function pklen[7:0] Packet Length.
  • Page 108 Si4330 Register 3Fh. Check Header 3 chhd[31:24] Name Type Reset value = 00000000 Name Function chhd[31:24] Check Header 3. byte of the check header. Register 40h. Check Header 2 chhd[23:16] Name Type Reset value = 00000000 Name Function chhd[23:16] Check Header 2.
  • Page 109 Si4330 Register 42h. Check Header 0 chhd[7:0] Name Type Reset value = 00000000 Name Function chhd[7:0] Check Header 0. byte of the check header. Header Enable bytes 3 to 0 control which bits of the Check Header bytes are checked against the corresponding bits in the Received Header.
  • Page 110 Si4330 Register 45h. Header Enable 1 hden[15:8] Name Type Reset value = 00000000 Name Function hden[15:8] Header Enable 1. byte of the check header. Register 46h. Header Enable 0 hden[7:0] Name Type Reset value = 00000000 Name Function hden[7:0] Header Enable 0.
  • Page 111 Si4330 Register 48h. Received Header 2 rxhd[23:16] Name Type Reset value = 00000000 Name Function rxhd[23:16] Received Header 2. byte of the received header. Register 49h. Received Header 1 rxhd[15:8] Name Type Reset value = 00000000 Name Function rxhd[15:8] Received Header 1.
  • Page 112 Si4330 Register 4Bh. Received Packet Length rxplen[7:0] Name Type Reset value = 11111111 Name Function rxplen[7:0] Length Byte of the Received Packet during fixpklen = 0 . (Specifies the number of Data bytes in the last received packet) This will be relevant ONLY if fixpklen (address 33h, bit[3]) is low during the receive time.
  • Page 113 Si4330 Register 50h. Analog Test Bus Select Reserved atb[4:0] Name Type Reset value = 00000000 Name Function Reserved Reserved. atb[4:0] Analog Test Bus. The selection of internal analog testpoints that are muxed onto TESTp and TESTn. Preliminary Rev 0.2...

  • Page 114: Table 32. Internal Analog Signals Available On The Analog Test Bus

    Si4330 Table 32. Internal Analog Signals Available on the Analog Test Bus atb[4:0] GPIOx GPIOx MixIp MixIn MixQp MixQn PGA_Ip PGA_In PGA_QP PGA_Qn ADC_vcm ADC_vcmb ADC_ipoly10u ADC_ref ADC_Refdac_p ADC_Refdac_n ADC_ipoly10 ADC_ipoly10 ADC_Res1Ip ADC_Res1In ADC_Res1Qp ADC_Res1Qn Reserved Reserved Reserved Reserved Reserved...

  • Page 115: Table 33. Internal Digital Signals Available On The Digital Test Bus

    Si4330 Register 51h. Digital Test Bus Select Reserved ensctest dtb[5:0] Name Type Reset value = 00000000 Name Function Reserved Reserved. ensctest Scan Test Enable. When set to 1 then GPIO0 will be the ScanEn input. dtb[5:0] Digital Test Bus. GPIO must be configured to Digital Test Mux output.
  • Page 116 Si4330 Table 33. Internal Digital Signals Available on the Digital Test Bus (Continued) dtb[4:0] GPIO0 Signal GPIO1 Signal GPIO2 Signal chip ready: READY state pll_en PLL enable: TUNE state tx_en TX enable: TX state ts_en temperature sensor enable auto_tx_on automatic TX ON...
  • Page 117 Si4330 The total settling time (cold start) of the PLL after the calibration can be calculated as T Register 53h. PLL Tune Time pllts[4:0] pllt0 Name Type Reset value = 01010010 Name Function pllts[4:0] PLL Soft Settling Time (T This register will set the settling time for the PLL from a previous locked frequency in Tune mode.
  • Page 118 Si4330 Register 55h. Calibration Control Reserved xtalstarthalf adccaldone enrcfcal rccal vcocaldp vcocal skipvco Name Type Reset value = x1x00100 Name Function Reserved Reserved. xtalstarthalf If Set, the Xtal Wake Time Period is Halved. adccaldone Delta-sigma ADC Calibration Done. Reading this bit gives 1 if the calibration process has been finished.
  • Page 119 Si4330 Register 56h. Modem Test bcrfbyp slicfbyp dttype oscdeten ookth refclksel refclkinv distogg Name Type Reset value = 00000000 Name Function bcrfbyp If set, BCR phase compensation will be bypassed. slicfbyp If set, slicer phase compensation will be bypassed. dttype Dithering Type.
  • Page 120 Si4330 Register 57h. Charge Pump Test pfdrst fbdiv_rst cpforceup cpforcedn cdonly cdcurr[2:0] Name Type Reset value = 00000000 Name Function pfdrst Direct Control to Analog. fbdiv_rst Direct Control to Analog. cpforceup Charge Pump Force Up. cpforcedn Charge Pump Force Down.
  • Page 121 Si4330 Register 59h. Divider Current Trimming/Delta-Sigma Test Reserved fbdivhc d3trim[1:0] d2trim[1:0] d1p5trim[1:0] Name Type Reset value = 10000000 Name Function Reserved Reserved. fbdivhc Feedback (fractional) Divider High Current Enable (+5 µA). d3trim[1:0] Divider 3 Current Trim Value. d2trim[1:0] Divider 2 Current Trim Value.
  • Page 122 Si4330 Register 5Bh. VCO Calibration/Override vcocalov/vcdone vcocal[6:0] Name Type Reset value = 00000000 Name Function vco- VCO Calibration Override/Done. calov/vcdone When vcocalov = 0 the internal VCO calibration results may be viewed by reading the vcocal register. When vcocalov = 1 the VCO results may be overridden externally through the SPI by writing to the vcocal register.
  • Page 123 Si4330 Register 5Dh. Block Enable Override 1 enmix enina enpga Reserved enbf5 endv32 enbf12 enmx2 Name Type Reset value = 00000000 Name Function enmix Mixer Enable Override. enlna LNA Enable Override. enpga PGA Enable Override. Reserved Reserved. enbf5 Buffer 5 Enable Override.
  • Page 124 Si4330 Register 5Fh. Block Enable Override 3 enfrdv endv31 endv2 endv1p5 dvbshunt envco encp enbg Name Type Reset value = 00000000 Name Function enfrdv Fractional Divider Enable Override. endv31 Divider 3_1 Enable Override. endv2 Divider 2 Enable Override. endv1p5 Divider 1.5 (div-by-1.5) Enable Override.
  • Page 125 Si4330 Register 61h. Channel Filter Coefficient Value Reserved chfilval[5:0] Name Type Reset value = 00000000 Name Function Reserved Reserved. chfilval[5:0] Filter Coefficient Value in the Look-up Table Addressed by the chfiladd[3:0]. Register 62h. Crystal Oscillator/Power-on-Reset Control pwst[2:0] clkhyst enbias2x enamp2x...
  • Page 126 Si4330 Register 63h. RC Oscillator Coarse Calibration/Override rccov rcc[6:0] Name Type Reset value = 00000000 Name Function rccov RC Oscillator Coarse Calibration Override. When rccov = 0 the internal Coarse Calibration results may be viewed by reading the rcccal register. When rccov = 1 the Coarse results may be overridden externally through the SPI by writing to the rcccal register.
  • Page 127 Si4330 Register 65h. LDO Control Override enspor enbias envcoldo enifldo enrfldo enpllldo endigldo endigpwdn Name Type Reset value = 10000001 Name Function enspor Smart POR Enable. enbias Bias Enable. envcoldo VCO LDO Enable. enifldo IF LDO Enable. enrfldo RF LDO Enable.
  • Page 128 Si4330 Register 67h. Delta-Sigma ADC Tuning 1 adcrst enrefdac enadc adctuneovr adctune[3:0] Name Type Reset value = 00011101 Name Function adcrst Delta-Sigma ADC Reset. enrefdac Delta-Sigma ADC Reference DAC Enable Override. enadc Delta-Sigma ADC Enable Override. adctuneovr Resonator RC Calibration Value Override Enable.
  • Page 129 Si4330 Register 69h. AGC Override 1 Reserved agcen lnagain pga[3:0] Name Type Reset value = 00100000 Name Function Reserved Reserved. agcen Automatic Gain Control Enable. When this bit is set then the result of the control can be read out from bits [4:0], otherwise the gain can be controlled manually by writing into bits [4:0].
  • Page 130 Si4330 Register 6Fh. TX Data Rate 0 txdr[7:0] Name Type Reset value = 00111101 Name Function txdr[7:0] Data Rate Lower Byte. See formula above. Defaults = 40 kbps. Register 70h. Modulation Mode Control 1 Reserved Reserved enphpwdn manppol enmaninv enmanch...
  • Page 131 Si4330 Register 71h. Modulation Mode Control 2 Reserved Reserved eninv fd[8] Reserved Name Type Reset value = 00000000 Name Function Reserved Reserved. eninv RX Data. fd[8] MSB of Frequency Deviation Setting, see "Register 72h. Frequency Deviation". Reserved Reserved. The frequency deviation can be calculated: Fd = 625 Hz x fd[8:0].
  • Page 132 Si4330 Register 72h. Frequency Deviation fd[7:0] Name Type Reset value = 00100000 Name Function fd[7:0] Frequency Deviation Setting. See formula above. Note: It's recommended to use modulation index of 1 or higher (maximum allowable modulation index is 32). The modulation...
  • Page 133 Si4330 Register 74h. Frequency Offset 2 Reserved fo[9:8] Name Type Reset value = 00000000 Name Function Reserved Reserved. fo[9:8] Upper Bits of the Frequency Offset Setting. fo[9] is the sign bit.The frequency offset can be calculated as Offset = 156.25 Hz x (hbsel + 1) x fo[7:0].
  • Page 134 Si4330 Register 76h. Nominal Carrier Frequency fc[15:8] Name Type Reset value = 10111011 Name Function fc[15:8] Nominal Carrier Frequency Setting. See formula above. Register 77h. Nominal Carrier Frequency fc[7:0] Name Type Reset value = 10000000 Name Function fc[7:0] Nominal Carrier Frequency Setting.
  • Page 135 Si4330 Register 79h. Frequency Hopping Channel Select fhch[7:0] Name Type Reset value = 00000000 Name Function fhch[7:0] Frequency Hopping Channel Number. Register 7Ah. Frequency Hopping Step Size fhs[7:0] Name Type Reset value = 00000000 Name Function fhs[7:0] Frequency Hopping Step Size in 10 kHz Increments.
  • Page 136 Si4330 Register 7Bh. Turn Around and 15.4 Length Compliance 15.4 Length Reserved[6:3] turn_around_en phase[1:0] Name Type Reset value = 01111011 Name Function 15.4 Length 15.4 Packet Length Compliance. If set, then PK Length definition for both TX and RX will also include the CRC bytes, If reset, then the Length refers ONLY to the DATA payload.
  • Page 137 Si4330 Register 7Fh. FIFO Access fifod[7:0] Name Type Reset value = NA Name Function fifod[7:0] FIFO Data. A Read (R/W = 0) to this address will begin a burst read of the RX FIFO. Preliminary Rev 0.2...

  • Page 138: Pin Descriptions: Si4330

    SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. PADDLE_GND The exposed metal paddle on the bottom of the Si4330 supplies the RF and circuit ground(s) for the entire chip. It is very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4330.

  • Page 139: Ordering Information

    Si4330 14. Ordering Information Part Description Package Operating Number* Type Temperature Si4330-A0-FM ISM EZRadioPRO Receiver QFN-20 –40 to 85 °C Pb-free *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.

  • Page 140: Package Information

    Si4330 15. Package Information Figure 34 illustrates the package details for the Si4330, and Figure 35 illustrates the landing pattern details. Figure 34. QFN-20 Package Dimensions 7 & : % (% & ) % + & % % (% & ) % % &...
  • Page 141 Si4330 OCUMENT HANGE Revision 0.1 to Revision 0.2 Updated register descriptions  Preliminary Rev 0.2...

  • Page 142: Contact Information

    Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur.

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