Silicon Laboratories Si4330 Manuals

Manuals and User Guides for Silicon Laboratories Si4330. We have 1 Silicon Laboratories Si4330 manual available for free PDF download: Manual

Silicon Laboratories Si4330 Manual (142 pages)

ISM RECEIVER

Brand: Silicon Laboratories | Category: Receiver | Size: 1 MB

Table of Contents
3
Electrical Specifications
7
Table 1. DC Characteristics
7
Table 2. Synthesizer AC Electrical Characteristics
8
Table 3. Receiver AC Electrical Characteristics
9
Table 4. Auxiliary Block Specifications
10
Table 5. Digital IO Specifications (SDO, SDI, SCLK, Nsel, and Nirq)
11
Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)
11
Table 7. Absolute Maximum Ratings
12
Definition of Test Conditions
13
Functional Description
14
Figure 1. RX Application Example
14
Operating Modes
15
Table 8. Operating Modes
15
Controller Interface
16
Serial Peripheral Interface (SPI)
16
Figure 2. SPI Timing
16
Table 9. Serial Interface Timing Parameters
16
Figure 3. SPI Timing-READ Mode
17
Figure 4. SPI Timing-Burst Write Mode
17
Figure 5. SPI Timing-Burst Read Mode
17
Operating Mode Control
18
Figure 6. State Machine Diagram
18
Table 10. Operating Modes
18
Interrupts
21
Device Code
21
System Timing
22
Figure 7. RX Timing
22
Frequency Control
23
Table 11. Frequency Band Selection
24
Figure 8. Frequency Deviation
26
Figure 9. Sensitivity at 1% PER Vs. Carrier Frequency Offset
27
Modulation Options
29
FIFO Mode
29
Internal Functional Blocks
30
Rx Lna
30
RX I-Q Mixer
30
Programmable Gain Amplifier
30
Adc
30
Digital Modem
30
Synthesizer
31
Figure 10. PLL Synthesizer Block Diagram
31
Crystal Oscillator
32
Regulators
32
Data Handling and Packet Handler
33
Rx Fifo
33
Figure 11. FIFO Threshold
33
Packet Configuration
34
Packet Handler RX Mode
34
Figure 12. Packet Structure
34
Figure 13. Required RX Packet Structure with Packet Handler Disabled
34
Figure 14. Multiple Packets in RX Packet Handler
35
Figure 15. Multiple Packets in RX with CRC or Header Error
35
Table 12. RX Packet Handler Configuration
35
Table 13. Packet Handler Registers
36
Data Whitening, Manchester Encoding, and CRC
37
Preamble Detector
37
Preamble Length
37
Figure 16. Operation of Data Whitening, Manchester Encoding, and CRC
37
Invalid Preamble Detector
38
Table 14. Minimum Receiver Settling Time
38
RX Modem Configuration
39
Modem Settings for FSK and GFSK
39
Table 15. RX Modem Configurations for FSK and GFSK
39
Table 16. Filter Bandwidth Parameters
41
Modem Settings for OOK
42
Table 17. Channel Filter Bandwidth Settings
42
Table 18. Ndec[2:0] Settings
43
Table 19. RX Modem Configuration for OOK with Manchester Disabled
44
Table 20. RX Modem Configuration for OOK with Manchester Enabled
44
Auxiliary Functions
45
Smart Reset
45
Figure 17. por Glitch Parameters
45
Table 21. por Parameters
45
Microcontroller Clock
46
General Purpose ADC
47
Figure 18. General Purpose ADC Architecture
47
Figure 19. ADC Differential Input Example-Bridge Sensor
48
Figure 20. ADC Differential Input Offset for Sensor Offset Coarse Compensation
49
Temperature Sensor
50
Table 22. Temperature Sensor Range
50
Figure 21. Temperature Ranges Using ADC8
51
Low Battery Detector
52
Wake-Up Timer
53
Figure 22. WUT Interrupt and WUT Operation
54
Low Duty Cycle Mode
55
Figure 23. Low Duty Cycle Mode
55
GPIO Configuration
56
Antenna-Diversity
57
Table 23. Antenna Diversity Control
57
RSSI and Clear Channel Assessment
58
Figure 24. RSSI Value Vs. Input Power
58
Reference Design
59
Figure 25. Receiver-Schematic
59
Table 24. Receiver Bill of Materials
60
Figure 26. Receiver-Top
61
Figure 27. Receiver-Top Silkscreen
61
Figure 28. Receiver-Bottom
62
Measurement Results
63
Figure 29. Sensitivity Vs. Data Rate
63
Figure 30. Receiver Selectivity
64
Figure 31. Synthesizer Settling Time for 1 Mhz Jump Settled Within 10 Khz
65
Figure 32. Synthesizer Phase Noise (VCOCURR = 11)
65
Application Notes
66
Crystal Selection
66
Layout Practice
66
Table 25. Recommended Crystal Parameters
66
Matching Network Design
67
Figure 33. RX LNA Matching
67
Table 26. RX Matching for Different Bands
67
Reference Material
68
Complete Register Table and Descriptions
68
Table 27. Register Descriptions
68
Table 28. Interrupt or Status 1 Bit Set/Clear Description
73
Table 29. When Are Individual Status Bits Set/Cleared if Not Enabled as Interrupts
73
Table 30. Interrupt or Status 2 Bit Set/Clear Description
75
Table 31. Detailed Description of Status Registers When Not Enabled as Interrupts
75
Table 32. Internal Analog Signals Available on the Analog Test Bus
114
Table 33. Internal Digital Signals Available on the Digital Test Bus
115
Pin Descriptions: Si4330
138
Ordering Information
139
Package Information
140
Figure 34. QFN-20 Package Dimensions
140
Figure 35. QFN-20 Landing Pattern Dimensions
140
Contact Information
142

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