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STS: T
ABLES OF STATES
(1)
REGISTER
NUMBER
ADDRESS
1
0
2
1
(1)
The register number n must be addressed n-1 in the data packet.
(2)
The bit number n must be addressed n-1 in the data packet.
- ENGLISH -
,
,
MEASUREMENTS
STS/ATS - STATES
Sound Off
Test in progress
Reserved
Reserved
Aux. Power2 failure
Aux. Power1 failure
Synchron bad
Preferred Source
Transfer inhibit
Non Synch. inhibit
Source S2 bad
Source S1 bad
On Source S2
On Source S1
ATS/STS Locked
Output Switch Off
S2 Black Out
Always zero
S2 Phase sequency not OK
S2 Voltage out of tolerance
S1 SCR alternance loss
S1 Input SW Off
S1 Frequency bad
S1 Balance bad
S1 Black Out
Always zero
S1 Phase sequency not OK
S1 Voltage out of tolerant
User Login
Alarm Overtemp.
Alarm Overload
General Failure
- 38 -
NOMINAL DATA AND COMMANDS
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=S1 / 1=S2]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
[0=No / 1=Yes]
(2)
BIT
NUMBER
ADDRESS
1
0
2
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
11
10
12
11
13
12
14
13
15
14
16
15
17
16
18
17
19
18
20
19
21
20
22
21
23
22
24
23
25
24
26
25
27
26
28
27
29
28
30
29
31
30
32
31
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