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SPI FLASH
+3.3V_MEMC
IC902
W25X20AVSNIG
R925
56
CS
VCC
M_SPI_CZ
1
8
R926
56
DO
HOLD
M_SPI_DO
2
7
R947
56
W P
CLK
WP_FLASH_MEMC
3
6
R948
56
GND
DIO
4
5
+1.26V_MEMC
+3.3V_MEMC
R949
1K
MEMC_SDA
MEMC_SCL
R950
1K
OPT
URSAII LVDS TYPE
VENUS (MST7329N)
URSAII MINI LVDS TYPE
M+S NORMAL 42"(MST7327N)
URSAII MINI LVDS TYPE
M+S NORMAL 47"(MST7327N)
URSAII MINI LVDS TYPE
M+S GIP 37"(MST7327N)
+3.3V_MEMC
L902
BLM18PG121SN1D
+1.8V_FRC_DDR
Placed on SMD-TOP
CONTACT TO MODULE FOR EMI
M2
MDS62110201
URSA_DQM3
URSA_DQM2
URSA_DQS2
URSA_DQSB2
M4
OPT
MDS62110201
URSA_DQS3
URSA_DQSB3
M5
MDS62110201
M6
MDS62110201
M7
+3.3V_MEMC
MDS62110201
URSA_MCLK
BLM18PG121SN1D
URSA_MCLKZ
L903
URSA_ODT
XTAL
R934
1M
M_XTALO
M_XTALI
X900
12MHz
C902
20pF
C900
20pF
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
M_SPI_CK
M_SPI_DI
+3.3V_MEMC
+3.3V_MEMC_AVDD
BLM18PG121SN1D
Placed on SMD-TOP
L904
R992
100
SDAS
E1
100
SCLS
R993
D1
GPIO[8]
F1
GPIO[9]
G1
GND_14
+3.3V_MEMC
K8
VDDC_1
GPIO12
GPIO14
E5
011:AG22
GPIO[10]
BIT_SEL
E2
GPIO[11]
F2
LVDS_SEL
LOW
LOW
GPIO[12]
F3
GPIO[13]
G2
GPIO[22]
LOW
M4
HIGH
GPIO[23]
M5
GPIO[14]
G3
HIGH
LOW
GPIO[15]
E4
GPIO[16]
F4
GPIO[17]
G4
HIGH
HIGH
GPIO[18]
H4
GPIO[19]
J 4
GPIO[20]
K4
GPIO[21]
L4
VDDP_2
J 6
GND_7
H9
GND_15 K9
VDDC_2
F6
URSA_DQ[20]
MDATA[20]
H1
URSA_DQ[19]
MDATA[19]
H2
URSA_DQ[17]
MDATA[17]
H3
URSA_DQ[22]
MDATA[22]
J 1
URSA_DQ[27]
MDATA[27]
J 2
URSA_DQ[28]
MDATA[28]
J 3
URSA_DQ[25]
MDATA[25]
K1
URSA_DQ[30]
MDATA[30]
K2
AVDD_DDR_2
K6
DQM[3]
K3
DQM[2]
L1
GND_10
J 8
DQS[2]
L2
DQSB[2]
L3
AVDD_DDR_4
L6
VDDP_3
L8
GND_8
H10
DQS[3]
M1
DQSB[3]
M2
AVDD_DDR_5
L7
URSA_DQ[31]
MDATA[31]
M3
URSA_DQ[24]
MDATA[24]
N1
GND_11
J 9
URSA_DQ[26]
MDATA[26]
N2
MDATA[29]
URSA_DQ[29]
N3
AVDD_DDR_6
L10
URSA_DQ[23]
MDATA[23]
P1
URSA_DQ[16]
MDATA[16]
R1
URSA_DQ[18]
MDATA[18]
T1
URSA_DQ[21]
MDATA[21]
T2
MCLK[0]
R2
MCLKZ[0]
P2
GND_1
G7
AVDD_MEMPLL
L9
MVREF
N5
ODT
N4
R928
R929
100
100
R931
R930
100
100
R935
R936
+3.3V_MEMC
100
100
R945
R946
BLM18PG121SN1D
100
100
R938
R939
L905
100
100
R942
R943
100
100
[ E 1 ]
[ D 1 ]
IC900
LGE7329A
[ L 9 ]
[ N 5 ]
[ N 4 ]
+3.3V_MEMC_AVDD
R954
C907
10uF
C905
820
10uF
10V
V4 LGD BIT SEL
GPIO_5
D8
H o r N C : 1 0 b i t
GPIO_7
D10
L : 8 b i t
GPIO_11
E10
GPIO_10
E3
R955
GPIO_3
BIT_SEL
D2
22 OPT
LVB2P
URSA_B2P
C15
LVB2M
URSA_B2M
B15
L908
LVBCKP
URSA_BCKP
A15
BLM18PG121SN1D
LVBCKM
URSA_BCKM
A16
OPT
OPC_OUT2
L909
LVB3P
URSA_B3P
B16
BLM18PG121SN1D
LVB3M
URSA_B3M
C16
OPC_EN
LVB4P
URSA_B4P
D15
L910
LVB4M
URSA_B4M
D16
BLM18PG121SN1D
AVDD_33_2
F9
OPC_OUT1
GND_4
G10
L911
LVC0P
URSA_C0P
E15
BLM18PG121SN1D
LVC0M
URSA_C0M
E16
PWM_DIM
LVC1P
URSA_C1P
E14
LVC1M
URSA_C1M
F14
R967
LVC2P
URSA_C2P
LVDS_SEL
F16
LVC2M
URSA_C2M
OPT
OPT
OPT
OPT
F15
LVCCKP
URSA_CCKP
G15
LVCCKM
URSA_CCKM
G16
LVC3P
URSA_C3P
G14
LVC3M
URSA_C3M
H14
LVC4P
URSA_C4P
H16
LVC4M
URSA_C4M
H15
LVD0P
URSA_D0P
V4 LGD LVDS SEL
J 1 5
LVD0M
URSA_D0M
J 1 6
L o r N C : V E S A
LVD1P
URSA_D1P
J 1 4
H : J E I D A
LVD1M
URSA_D1M
K14
V4 LGD OPC
GND_3
G9
L or NC : DISABLE
LVD2P
URSA_D2P
L14
H : ENABLE
LVD2M
URSA_D2M
L15
LVDCKP
URSA_DCKP
L16
LVDCKM
URSA_DCKM
M16
AVDD_33_1
F8
LVD3P
URSA_D3P
M15
LVD3M
URSA_D3M
M14
LVD4P
URSA_D4P
N16
LVD4M
URSA_D4M
N15
VDDC_5
H6
+3.3V_MEMC
GPIO[24]
N6
GPIO[7]
E12
GPIO[6]
D14
GPIO[5]
F12
GPIO[4]
E13
GPIO[3]
F13
GPIO[2]
G13
GPIO[1]
H13
GPIO[0]
J 1 3
PWM0
K12
PWM1
[ N 1 3 ]
L12
CSZ
K13
[ N 1 2 ]
M_SPI_CZ
SDO
M12
M_SPI_DO
SDI
M13
M_SPI_DI
SCK
L13
M_SPI_CK
GPIO[30]
N14
GPIO[29]
N13
GPIO[28]
N12
OPT
R933
0
WP_FLASH_MEMC
GPIO8
PWM1
I2C
HIGH
LOW
+3.3V_MEMC
EEPROM
HIGH
HIGH
SPI
HIGH
HIGH
MEMC_RESET
I S P P o r t f o r F R C
P902
12507WR-04L
URSA_DQ[0-31]
OPT
EAX60890801
FRC
PANEL_POWER
C953
C951
100uF
16V
0 . 1 u F
P900
TF05-51S
1
2
3
4
5
6
7
8
9
10
URSA_B4M
11
+3.3V_MEMC
URSA_B4P
12
URSA_B3M
13
URSA_B3P
14
15
URSA_BCKM
16
URSA_BCKP
17
18
URSA_B2M
19
URSA_B2P
20
URSA_B1M
21
URSA_B1P
22
URSA_B0M
23
URSA_B0P
24
25
26
URSA_A4M
27
URSA_A4P
28
URSA_A3M
29
URSA_A3P
30
31
URSA_ACKM
32
URSA_ACKP
33
34
URSA_A2M
35
URSA_A2P
36
URSA_A1M
37
URSA_A1P
38
URSA_A0M
39
URSA_A0P
40
41
42
43
44
45
22 OPT
46
OPT
OPT
OPT
OPT
47
48
49
50
51
52
P901
TF05-41S
1
2
URSA_D4M
3
URSA_D4P
4
URSA_D3M
5
URSA_D3P
6
7
URSA_DCKM
8
URSA_DCKP
9
10
URSA_D2M
11
URSA_D2P
12
URSA_D1M
13
URSA_D1P
14
URSA_D0M
15
URSA_D0P
16
17
18
URSA_C4M
19
URSA_C4P
20
URSA_C3M
21
URSA_C3P
22
23
URSA_CCKM
24
URSA_CCKP
25
26
URSA_C2M
27
URSA_C2P
28
URSA_C1M
29
URSA_C1P
30
URSA_C0M
31
URSA_C0P
32
33
34
35
36
37
38
39
40
41
42
PWM0
HIGH
LOW
HIGH
1
2
3
MEMC_SCL
0 0 1 : E 2 0 ; 0 1 1 : I 2 2
4
MEMC_SDA
0 0 1 : E 2 0 ; 0 1 1 : I 2 2
5
2 0 0 9 . 0 4 . 1 6
9
12
LGE Internal Use Only
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