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Circuit Descriptions, Abbreviation List and Data Sheets
9.8.4
Diagram N1, SAA2505 (IC7801)
Internal Block Diagram and Pinning
2
I
S-bus
interface
bitstream
IIS0
bitstream
e.g. from
IIS1
microphone
STANDALONE
IEC 1397
PARSER
MPEG2
OR
AC-3
DECODER
PCM
AND
DOWN-
SAMPLING
1
EFO1
2
EFO2
3
EFO3
4
EFO4
5
EFO5
6
EFO6
7
V SSDI
8
V DDDI
9
EFI1
10
EFI2
11
EFI3
12
V DDDE
13
WSO
14
SCK
15
V SSDE
16
L
8 channels
R
C
LFE
LT, RT
LS
PRO LOGIC
RS
LC
SWITCH
RC
channels
NOISE
1 to 8
GENERATOR
microphone
bitstream
Simplified block diagram.
SAA2505H
Pin configuration.
Figure 9-20
MG3.2E
9.
DELAY
audio clock
256 or 384f s
L, R, C, S
DOWN-
MIXING
channels
AND
1 to 8
VOLUME
CONTROL
OUTPUTS
8 channels
L, R
DOWN-
MIXING
48
TMS
47
TDI
V SSDE
46
45
ACLK
V SSDA
44
43
CLKO
42
CLKI
V DDA
41
V DDDE
40
SYSCLK
39
V SSDE
38
V DDDI
37
V SSDI
36
V SSDE
35
34
SPDIF
33
SDB
MGL323
CL 16532149_112.eps
EN 159
2
I
S-BUS
SPDIF
MGL324
201201
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