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CMOSTEK CMT2189B User Manual

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AN201
AN201
CMT2189B User Guide
Overview
The CMT2189B is a low power, high performance, Flash-based, OOK RF transmitter chip embedded with the RISK MCU , which
TM
covers a wireless communication band of 240 - 960 MHz. The product is a part of the CMOSTEK NextGenRF
product family
which covers a complete product line consisting of transmitters, receivers, transceiver, etc.
The product models covered in this document are shown in the table below.
Table 1. Product Models Covered in This Document
Product
Frequency
Modulation
Tx Power
Tx Current
Configuration
Package
Model
Range
Method
Embedded
CMT2189B
240 - 960MHz
OOK
+13 dBm
17.5 mA
SOP14
MCU
Notes:
The test condition for the Tx power and Tx current is: 433.92 MHz, CW mode (always in the Tx carrier mode), Tx mode of Duty 50%
and Tx current of 8.5 mA.
©
Rev 1.5 | 1/91
www.cmostek.com
Copyright
By CMOSTEK

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Summary of Contents for CMOSTEK CMT2189B

  • Page 1 Overview The CMT2189B is a low power, high performance, Flash-based, OOK RF transmitter chip embedded with the RISK MCU , which covers a wireless communication band of 240 - 960 MHz. The product is a part of the CMOSTEK NextGenRF product family which covers a complete product line consisting of transmitters, receivers, transceiver, etc.

  • Page 2: Table Of Contents

    TMR0 (Addr:0x01) ........................... 36 4.1.4 STATUS (Addr:0x03)..........................36 4.1.5 PORTA (Addr:0x05) ..........................38 4.1.6 PORTC（Addr:0x07） ..........................38 4.1.7 INTCON (Addr:0x0B) ..........................39 4.1.8 PIR1 (Addr:0x0C)............................. 40 4.1.9 TMR2 (Addr:0x11) ............................ 41 4.1.10 T2CON (Addr:0x12) ..........................41 Rev 1.5 | 2/91 www.cmostek.com...
  • Page 3 6 Reset Timing ............................ 62 6.1 Power-on Reset (POR) ............................ 63 6.2 MCLR External Reset (MCLR) ......................... 63 6.3 Power-up Timer (PWRT) ..........................63 6.4 Brown-out Reset / Low Voltage Reset ......................63 6.5 Error Instruction Reset ............................. 64 Rev 1.5 | 3/91 www.cmostek.com...
  • Page 4 16.3.1 PORTA<2:0> ............................83 16.3.2 PORTA3/PA3 ............................84 16.3.3 PORTA4/PA4 ............................85 16.3.4 PORTA5/PA5 ............................86 16.3.5 PORTA7/PA7 ............................86 16.3.6 PORTC<7:0> ............................87 17 Instruction Set ..........................88 18 Revise History ..........................90 19 Contacts ............................91 Rev 1.5 | 4/91 www.cmostek.com...

  • Page 5: Chip Architecture

    1.1 Overall Operating Principle The CMT2189B is a RF transmitting chip integrated with digital and analog parts altogether, which applies a crystal oscillator to provide the reference frequency and digital clock for PLL, supporting OOK modulation with a data rate range of 1 ~ 40 kbps. It supports status control through the MCU programming to fulfill various low power transmission applications.
  • Page 6 AN201 Table 2. CMT2189B Pin Description - SOP14 Package Pin # Pin Name Type Description DVDD Digital Chip power supply + General purpose IO Digital General purpose IO PC4/C2OUT Digital Comparator 2 output C2OUT XTAL Analog Crystal oscillator input in RF part SPI interface enabling control in RF part, low active, internal pull up.
  • Page 7 PC<3:0> is the internal control pin of the chip, which has no package pin, but it is used as a bus controlling RF part internally. Rev 1.5 | 7/91 www.cmostek.com...

  • Page 8: Rf Part Configuration And Control Mechanism

    2 RF Part Configuration and Control Mechanism 2.1 Operating Mode The built-in OOK Tx function of the CMT2189B supports 2 operating modes.  Simple operating mode: the default entry mode upon power-up, namely, the non-configuration mode, which supports the pass-through Tx mode only.

  • Page 9: Advanced Configuration Mode

    PC1/SDIO is used as the serial data line of SPI. With both using the register configuring method, the pass-through mode in advanced configuration mode can support more frequency selection and power selection than that in the simple operating mode. Rev 1.5 | 9/91 www.cmostek.com...

  • Page 10: Spi Interface Timing

    8 clock. > 0. 5 SCLK cycle > 0. 5 SCLK cycle RFCTRL PC3/CSB PC2/SCLK PC / SDIO r/ w = 1 register address register read data Figure 4. SPI Read Register Timing Rev 1.5 | 10/91 www.cmostek.com...

  • Page 11: Rf Configuration Parameter

    RFCTRL is an input port requiring external control. It is recommended that users control it through any function port in the CMT2189B, and pull it down to enable SPI interface function. In the whole process, RFCTRL can keep low, but in the low power sleep mode, it needs to set the MCU pin controlling RFCTRL to a high impedance input, since the pull-up inside RFCTRL can pull the level high.
  • Page 12 Export to generate an exp file with file content as follows. ;--------------------------------------- ; CMT2157B Configuration File ; Generated by CMOSTEK RFPDK 1.46 ; 2017.11.14 13:47 ;--------------------------------------- ; (Among them, the annotation part with ; is omitted.) ;---------------------------------------...
  • Page 13 ; The following is the CRC result for ; the above EEPROM contents ;--------------------------------------- 0xEDFA ;--------------------------------------- ; The following are for CMOSTEK ; use, customers can ignore them ;--------------------------------------- 0x0000 0x0018 Among them, the specific configuration content is with red font, which are all 16-bit Word with a total of 24 Words contained, therefore users need to convert the 16-bit Word to the format of 8-bit register content.

  • Page 14: Configuration Register

    Users only need to write the above contents (as parameters) into the 0x01～0x2E register address while writing timing through SPI. 2.6 Configuration Register The above exported configuration parameter address from 0x01 to 0x2E can be divided into three banks according to the functions, which are as follows: Rev 1.5 | 14/91 www.cmostek.com...

  • Page 15: Packet Related Register

    PREAMBLE_E 0x08 CUS_PKT1 TCYCLE_EN INTERVAL_EN STOP_EN KEY_EN SYNC_EN PREAMBLE_LOCATION PREAMBLE_SEL 0x09 CUS_PKT2 TXCYCLE<7:0> 0x0A CUS_PKT3 PREAMBLE_LENGTH<7:0> 0x0B CUS_PKT4 KEY_LENGTH<2:0> SYNC_LENGTH<4:0> 0x0C CUS_PKT5 SYNC_HEADER<7:0> 0x0D CUS_PKT6 SYNC_HEADER<15:8> 0x0E CUS_PKT7 SYNC_HEADER<23:16> 0x0F CUS_PKT8 SYNC_HEADER<31:24> 0x10 CUS_PKT9 ADDR_ID<7:0> Rev 1.5 | 15/91 www.cmostek.com...

  • Page 16: Tx Rate

    The blue area indicates that users need to understand it. The registers will be detailed one by one in below. The built-in packet structure pattern of the CMT2189B is the same as that of the CMT2157B. Users can select the packet structure of the CMT2157B in RFPDK configuration screen.

  • Page 17: Hardware Packet Format

    AN201 2.7.2 Hardware Packet Format The CMT2189B supports hardware packet structure internally with data frame structure as follows. Head/ Stop Preamble ID/ADDR Key Value Pause/Interval Sync Status Figure 7. Packet Structure As shown in the packet structure in the above figure, it contains 7 parts.

  • Page 18: Preamble

    CUS_PKT5 SYNC_HEADER<7:0]> (0x0C) CUS_PKT6 The value of sync can be filled in different registers SYNC_HEADER<15:8> (0x0D) according to the different SYNC_LENGTH settings, please refer the next table for details. CUS_PKT7 SYNC_HEADER<23:16> (0x0E) CUS_PKT8 SYNC_HEADER<31:24> Rev 1.5 | 18/91 www.cmostek.com...

  • Page 19: Addr/Id

    0 ~ 7. 0 represents 1 symbol and so on. 7 represents 8 symbols. CUS_PKT15 BIT_LOGIC_L<7:0> Logic 0 definition (0x16) CUS_PKT16 BIT_LOGIC_H<7:0> Logic 1definition (0x17) CUS_PKT9 ADDR_ID<7:0> (0x10) CUS_PKT10 ADDR_ID<15:8> (0x11) Addr ID value CUS_PKT11 ADDR_ID<23:16> (0x12) CUS_PKT12 ADDR_ID<31:24> (0x13) Rev 1.5 | 19/91 www.cmostek.com...
  • Page 20 0x5678. Then users will fill the value into ADDR_ID<31:24> and ADDR_ID<23:16> registers. MSB is corresponding to the 31 bit and LSB corresponds to the 16 bit, that is, 0x56 is filled into ADDR_ID<31:24> and 0x78 is filled into ADDR_ID<23:16>. Rev 1.5 | 20/91 www.cmostek.com...

  • Page 21: Key Value

    The key value length can be configured to 0~7. 0 represents sending a key of 1 logic bit, and so on. 7 CUS_PKT4 (0x0B) KEY_LENGTH<2:0> represents sending a Key of 8 logic bits.The logic bit length is random. CUS_PKT17 (0x18) KEY<7:0> Key Value Rev 1.5 | 21/91 www.cmostek.com...

  • Page 22: Lbd Status Configuration

    The voltage comparison threshold of the LBD. Iif the actual voltage is greater than the threshold, the LBD_TH<3:0> LBD result is 1 (logic 1), and conversely, it is 0 (logic 0). CUS_LBD_RESULT LBD_RESULT<3:0> Voltage measurement value (0x4B) Rev 1.5 | 22/91 www.cmostek.com...
  • Page 23 If LBD_OUT_EN is configured as 1, the LBD result will be sent out as part of the packet. See Section 2.7.1 for details. In the chip, the voltage value is converted by a 4-bit ADC to obtain LBD_RESULT with each step as 0.2 V. The relationship between the voltage value and LBD_RESULT is as follows. Rev 1.5 | 23/91 www.cmostek.com...

  • Page 24: Stop Bit Configuration

    The stop bit length can be configured to 0 ~ 15. 0 CUS_PKT14 represents sending a stop of 1 Symbol, and so on. 15 STOP_LENGTH<3:0> (0x15) represents sending a stop of16 symbols, The symbol length is random. CUS_PKT27 STOP_BIT<7:0> (0x22) STOP_BIT Value CUS_PKT28 STOP_BIT<15:8> (0x23) Rev 1.5 | 24/91 www.cmostek.com...

  • Page 25: Pause/Interval Configuration

    (N) repeated packet transmissions with the support of pause/interval between packets. It also supports transmitting m data groups in a transmission cycle with each data group composed of N packets. The different transmission cycle configurations are shown in the below figure. Rev 1.5 | 25/91 www.cmostek.com...
  • Page 26 0: In one cycle, each Packet contains 1 Preamble, i.e. PREAMBLE_LOCATION in one cycle, N Packets contain N Preambles. CUS_PKT1 1: In one cycle, only 1 Preamble is included, which is (0x08) only in the first Packet. Tcycle Enable bit: TCYCLE_EN 0：Disable 1：Enable Rev 1.5 | 26/91 www.cmostek.com...

  • Page 27: State And Function Register

    (CFG) is configured. 2.8.2 Operating State and State Switching The CMT2189B RF supports 3 major operating states. In advanced configuration mode, the states and state switching are shown in the below diagram. Rev 1.5 | 27/91...

  • Page 28: Operating State Query

    Table 25. State Switching Command and Reset Command Control Register Command Type Command Writing Value Function Description go_sleep 0x01 Return SLEEP state CUS_MODE State jumping go_tx 0x02 Enter TX state （0x33） go_stby 0x08 Enter STBY state 2.8.3 Operating State Query Rev 1.5 | 28/91 www.cmostek.com...

  • Page 29: Hardware Packet Tx Mode

    After initialization, the chip can enter low power based sleep state or perform other processing. 2.9.2 Tx Process The CMT2189B hardware data packet frame structure is shown in the below figure. Please refer to Section 2.7.2 for the data frame structure descriptions.
  • Page 30 The standby state cannot be judged by transmission completion since it's in standby state as well during the data packet interval. It should be noted that the internal pin state processing after transmission completion is different from the processing after power-up initialization. Rev 1.5 | 30/91 www.cmostek.com...

  • Page 31: Pass-Through Tx Mode (Advanced Configuration Mode)

    When the transmission is started up again, execute the Tx process once again. In step 3, 6, 1, 11, users need to use read-modify-write method to avoid modifying the value of other bits by mistake. 2.10.3 Related Register Rev 1.5 | 31/91 www.cmostek.com...
  • Page 32 PC0. Users need to consider the TX_OVERTIMES setting according to the encoding format. TX_OVERTIMES is set to 20 ms by default, and can increase to 90 ms by the step of 10 ms. Rev 1.5 | 32/91 www.cmostek.com...

  • Page 33: Program Memory

    User and factory configuration information bank is 0x2000 ~ 0x203F. 0x000 Program area 0x7FF 0x2000 UCFG0 0x2001 UCFG1 0x2002 UCFG2 Reserved Unusable 0x2010 FCFG0 0x2011 FCFG1 0x2012 FCFG2 0x2020 INFOx 0x1FFF 0x2000 Information area 0x203F 0x203F Figure 11. Program Space Address Mapping Rev 1.5 | 33/91 www.cmostek.com...

  • Page 34: Special Function Register(Sfr)

    - - - - - - - - - - - - - - - - WDTCON WDTPS<3:0> SWDTEN - - - 0 1 0 0 0 CMCON0 C2OUT C1OUT C2INV C1INV CM<2:0> 0000 0000 Rev 1.5 | 34/91 www.cmostek.com...

  • Page 35: Bank1 Sfr

    - - - - - - q q OSCCON LFMOD IRCF<2:0> OSTS 0101 x000 - - - - - - - - 0000 0000 PR2<7:0>, Timer2 period register 1111 1111 - - - - - - - - Rev 1.5 | 35/91 www.cmostek.com...

  • Page 36: Tmr0 (Addr:0X01)

    Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR0 Timer0<7:0>, counter result register Reset Type 4.1.4 STATUS (Addr:0x03) Table 30. STATUS Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 STATUS PAGE Reset Type Rev 1.5 | 36/91 www.cmostek.com...
  • Page 37 0 = bit 4 carrying/borrowing does not occur in the calculation result. Carrying/borrowing ( ADDWF, ADDLW, SUBLW and SUBWF instruction). 1 = carrying/borrowing occurs in the calculation result. 0 = carrying/borrowing does not occur in the calculation result. Rev 1.5 | 37/91 www.cmostek.com...

  • Page 38: Porta (Addr:0X05)

    PORTA5 only has input function. There is no corresponding output data register. PORTA4 data PORTA3 data PORTA2 data PORTA1 data PORTA0 data 4.1.6 PORTC（Addr:0x07） . PORTC Register Table 35 Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PORTC Reset Rev 1.5 | 38/91 www.cmostek.com...

  • Page 39: Intcon (Addr:0X0B)

    1 = enable the PORTA<7:0> change interrupt 0 = disable the PORTA<7:0> change interrupt Timer 0 overflow interrupt flag bit T0IF 1 = Timer 0 overflow occurs (must be cleared by software) 0 = Timer 0 overflow does not occur Rev 1.5 | 39/91 www.cmostek.com...

  • Page 40: Pir1 (Addr:0X0C)

    Timer 2 and PR2 compare matching interrupt flag bit. TMR2IF 1 = Timer 2 and PR2 matching occurs (must be cleared by software) 0 = Timer 2 and PR2 matching does not occur Reserved bit, cannot be written to 1. Rev 1.5 | 40/91 www.cmostek.com...

  • Page 41: Tmr2 (Addr:0X11)

    1 = Timer 2 is on 0 = Timer 2 is off Timer 2 driving clock dividing ratio selection bits. T2CKPS<1:0> 00 = 1:1 dividing ratio. 01 = 1:4 dividing ratio. 1x = 1:16 dividing ratio. Rev 1.5 | 41/91 www.cmostek.com...

  • Page 42: Wdtcon (Addr:0X18)

    1 = WDT is turned on 0 = WDT is turned off 4.1.12 CMCON0 (Addr:0x19) Table 46. CMCON0 Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CMCON0 C2OUT C1OUT C2INV C1INV CM<2:0> Reset Type Rev 1.5 | 42/91 www.cmostek.com...

  • Page 43: Pr0 (Addr:0X1A)

    101 = 1 independent comparator 110 = 2 common reference comparators with outputs 111 = the comparator is turned off, and the CxIN pin is the digital IO pin. 4.1.13 PR0 (Addr:0x1A) Table 48. PRO Register Rev 1.5 | 43/91 www.cmostek.com...

  • Page 44: Msckcon (Addr:0X1B)

    1 = enable measuring slow clock period using fast clock CKCNTI 0 = disable measuring slow clock period using fast clock. Notes: The bit will automatically return to 0 after the measurement is completed. Reserved bit, cannot be written to 1. 4.1.15 SOSCPR (Addr:0x1C/0x1D) Rev 1.5 | 44/91 www.cmostek.com...

  • Page 45: Option (Addr:0X81)

    1 = PA2/INT pin Interrupt triggered on the rising edge 0 = PA2/INT pin Interrupt triggered on the falling edge Timer 0 clock source selection bit T0CS 1 = select PA2/T0CKI 0 = select internal instruction cycle clock (FOSC/2) Rev 1.5 | 45/91 www.cmostek.com...

  • Page 46: Trisa (Addr:0X85)

    PORTA5 port direction control bit. TRISA<5> Input only, fixed to 1. PORTA<4:0> port direction control bits. TRISA<4:0> 1 = input 0 = output 4.1.18 TRISC (Addr:0x87) Table 59. TRISC Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Rev 1.5 | 46/91 www.cmostek.com...

  • Page 47: Pie1（Addr:0X8C

    Comparator 1 interrupt enabling bit. C1IE 1 = enable comparator 1 interrupt 0 = disable comparator 1 interrupt Oscillator failure interrupt enabling bit. OSFIE 1 = enable the oscillator failure interrupt 0 = disable the oscillator failure interrupt Rev 1.5 | 47/91 www.cmostek.com...

  • Page 48: Pcon（Addr:0X8E

    1 = no brown-out reset occurs or it is set to 1 by software. 4.1.21 OSCCON (Addr:0x8F) Table 65. OSCCON Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OSCCON LFMOD IRCF<2:0> OSTS Reset Type Rev 1.5 | 48/91 www.cmostek.com...

  • Page 49: Pr2 (Addr:0X92)

    Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PR2<7:0> Reset 0xFF Type . PR2 Bit Function Description Table 68 Name Function PR2<7:0> Timer 2 period (compare) register (see Timer 2 specific sections for details). Rev 1.5 | 49/91 www.cmostek.com...

  • Page 50: Wpua (Addr:0X95)

    1 = enable port state triggered interrupt 0 = disable port state triggered interrupt 4.1.25 VRCON (Addr:0x99) Table 73. VRCON Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 VRCON VREN VR<3:0> Reset Type Rev 1.5 | 50/91 www.cmostek.com...

  • Page 51: Eedat（Addr:0X9A

    Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EEADR EEADR<7:0> Reset 0x00 Type 4.1.28 EECON1（Addr:0x9C） Table 77. EECON1 Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EECON1 WREN3 WREN2 WRERR WREN1 Reset Type Rev 1.5 | 51/91 www.cmostek.com...

  • Page 52: Eecon2 (Addr:0X9D)

    The software cannot access UCFG0, UCFG1 and UCFG2. They can only be written by the hardware (programming) in the power up process.  UCFG0, PROM address 0x2000 . UCFG0 Configuration Register Table 81 Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UCFG0 MCLRE PWRTEB WDTE FOSC<2:0> Rev 1.5 | 52/91 www.cmostek.com...
  • Page 53 0 = disable Port read control bit in output mode RD_CTRL 1 = read the value of the PAD returned from the data port 0 = read the value of the Latch returned from the data port Rev 1.5 | 53/91 www.cmostek.com...

  • Page 54: Pcl And Pclath

    PCLATH is not required since the operating code in the instructions is 11-bit, and the chip PC is exactly 11-bit. ALU结果 OPCODE<10:0> PCLATH<2:0> PCLATH PCLATH Instruction with PCL as Instruction Target LJUMP and LCALL Instruction Figure 12. PC Loading in Different Situations Rev 1.5 | 54/91 www.cmostek.com...

  • Page 55: Indf And Fsr Register

    0 ~ 255. Any instruction using the INDF register actually accesses the unit that the file selection register FSR points to. Reading the INDF indirectly will return 0. Writing the INDF indirectly will cause the control operation (It may affect the state flag bit). Rev 1.5 | 55/91 www.cmostek.com...

  • Page 56: System Clock Source

    The internal clock mode is built in the oscillator module. The oscillator module has a 16 MHz high frequency oscillator and a 32 kHz low frequency oscillator. Internal or external clock sources can be selected by the system clock selection bit(SCS) of the OSCCON register. Rev 1.5 | 56/91 www.cmostek.com...

  • Page 57: External Clock Mode

    IRCF<2:0> is used to select the frequency output of the internal oscillator. Select 1 of the following 8 frequencies via the software.  16 MHz  8 MHz  4 MHz (Default value after reset)  2 MHz  1 MHz  500 kHz  250 kHz Rev 1.5 | 57/91 www.cmostek.com...

  • Page 58: Clock Switching Timing Of Hfintosc And Lfintosc

    Figure 15. Switch from Fast Clock to Slow Clock 5.4 Clock Switching Users can switch the system clock source between the external and internal clock sources by operating the system clock selection (SCS) bit of the OSCCON register via software. Rev 1.5 | 58/91 www.cmostek.com...

  • Page 59: System Clock Selection Bit (Scs)

    The two-speed start-up mode is configured by the following settings.  Configure the IESO bit in the Configuration Word register UCFG1 as 1, namely the internal/external switching bit (enable the two-speed start-up mode).  Configure the SCS bit of the OSCCON register as 0. Rev 1.5 | 59/91 www.cmostek.com...

  • Page 60: Two-Speed Start-Up Sequence

    The FSCM module detects the oscillator fault by comparing the external oscillator with the FSCM sampling clock. LFINTOSC divided by 64 is the sampling clock. See Figure 16 for details . There is a latch inside the fault detector. On each falling edge of Rev 1.5 | 60/91 www.cmostek.com...

  • Page 61: Fail-Safe Operation

    (e.g. after exiting reset or sleep). After an appropriate amount of time, users should check the OSTS bit of the OSCCON register to verify whether the oscillator has successfully started and whether the system clock has been switched successfully. Rev 1.5 | 61/91 www.cmostek.com...

  • Page 62: Reset Timing

    AN201 6 Reset Timing The CMT2189B supports several types of resets as follows. Power-on reset (POR) WDT reset during normal operating WDT wakeup during sleep MCLR pin reset during normal operating /MCLR pin reset during sleep Brown-out reset/low voltage reset (BOR/LVR) Some registers are not affected in any reset condition.

  • Page 63: Power-On Reset (Por)

    VDD is lower than the threshold on which the system can operate normally. If the reset signal is generated by the BOR circuit, the VDD voltage must keep for more than 100 us at the VSS level. Rev 1.5 | 63/91 www.cmostek.com...

  • Page 64: Error Instruction Reset

    1 and check whether it is 0 then. Bit 1 is the /POR indication bit, which is 0 upon power-on reset, and the software must set it to 1. POR_RSTN 4ms delay BOOT_EN PWRTE BOOT_END PWRT,64ms PWRT_OV MCLRB SYS_RSTN Figure 19. Power-on Reset with MCLRB Rev 1.5 | 64/91 www.cmostek.com...
  • Page 65 After the voltage is restored to normal, the internal reset will not be released immediately, but wait for about 8 ms instead. Table 87. Timeout in Various Cases Oscillator Power-on Reset Brown-out Reset Sleep Wake-up configuration /PWRTEB=0 /PWRTEB=1 /PWRTEB=0 /PWRTEB=1 INTOSC TPWRT TPWRT Rev 1.5 | 65/91 www.cmostek.com...
  • Page 66 AN201 Table 88. STATUS/PCON Bit Description (U: no change, X: unknown) /POR /BOR Condition WDT Reset WDT Wake-up /MCLR reset during normal operation /MCLR reset during sleep Rev 1.5 | 66/91 www.cmostek.com...

  • Page 67: Boot

    After POR or BOR, it inserts a state and maps the program EEPROM units starting from 2000H into configuration registers. The system reset is released until the end of the BOOT, as shown in Figure 19 and Figure 20. The process needs about 17 us. Rev 1.5 | 67/91 www.cmostek.com...

  • Page 68: Watchdog Timer

    If the internal slow clock switches from the 32 k to 256 k mode (or from the 256 k to 32 k mode), it does not affect the watchdog timing, as WDT is fixed to use the 32 k clock source. Rev 1.5 | 68/91 www.cmostek.com...

  • Page 69: Timer 0

    In this mode, Timer 0 increases by 1 (without prescaler) in each instruction cycle. The software can clear the T0CS bit of the OPTION register to enter the timer mode. When the software performs write operation to the TMR0, the timer will not increase in the following 2 cycles. Rev 1.5 | 69/91 www.cmostek.com...

  • Page 70: Counter Mode Of Timer 0

    OPTION_REG, PSA CLRWDT ；Mask prescaler bits LDWI b’11111000’ ANDWR OPTION_REG, W ；Set WDT prescaler to 1:32 IORWI b’00000101’ When switch the prescaler assignment from the WDT to TMR0, please execute the following instruction sequence. LDWI OPTION_REG Rev 1.5 | 70/91 www.cmostek.com...

  • Page 71: Timer 0 Interrupt

    In the counter mode, the synchronization between the T0CKI pin input and the Timer 0 register is fulfilled by sampling the phase of the internal clock Q1 and Q2, therefore the high level time and low level time of the external clock source cycle must meet the relevant timing requirement. Rev 1.5 | 71/91 www.cmostek.com...

  • Page 72: Timer 2

    Setting the TMR2ON bit of the T2CON register to 1 can enable Timer 2, and clearing the TMR2ON bit can disable Timer 2 on the contrary. The Timer 2 prescaler is controlled by the T2CKPS bit of the T2CON register. The Timer 2 postscaler is controlled by the TOUTPS bit of the T2CON register. Rev 1.5 | 72/91 www.cmostek.com...
  • Page 73 The prescaler counter and postscaler counter will be cleared when the following registers are written:  Write the TMR2  Write the T2CON  Any reset action Writing the T2CON does not clear the TMR2 register. Rev 1.5 | 73/91 www.cmostek.com...

  • Page 74: Comparator

    When the word D is marked on the port, users should set the corresponding TRIS bit to 0 to open the digital output driver circuit. In addition, the comparator interrupt should be disabled during the comparator configuration switching to avoid unexpected miss-triggered events. Rev 1.5 | 74/91 www.cmostek.com...

  • Page 75: Data Eeprom

    EECON1 register to 1. In the next cycle, the EEDAT register is written with the EEPROM data. Therefore, this data can be read by the next instruction. The EEDAT will keep this value until the user reads or writes the data of the unit the next time (during the write operation). Rev 1.5 | 75/91 www.cmostek.com...

  • Page 76: Clock Measurement

    After the end of the measurement, MSCKCON.1 is automatically cleared, and the interrupt flag is set to 1. Wait for the measurement completion in a query or interrupt manner. When the interrupt flag is checked to be 1, the read SOSCPR is the final result. Rev 1.5 | 76/91 www.cmostek.com...
  • Page 77 AN201 CKMAVG BUS<1> CKCNTI MSCKCON WR CKMEAS EN T2 SYSCLK MEAS DONE SYSCLK TMR2 16-bit SOSCPR<11:0> To INT Figure 26. Block Diagram for Slow Clock Measurement Mode Rev 1.5 | 77/91 www.cmostek.com...

  • Page 78: Interrupt Mode

    AN201 Interrupt Mode The CMT2189B supports the following interrupt sources:  External interrupt from the PA2/INT pin  Timer 0 overflow interrupt  PORTA change Interrupt  Timer 2 compare matching interrupt  EEPROM data write Interrupt  Slow clock measurement Interrupt The interrupt control register (INTCON) and peripheral interrupt request register (PIR1) record the interrupt flag bit.

  • Page 79: Porta Level Change Interrupt

    The interrupt delay of the external interrupts, including the interrupt from the INT pin or the PORTA change interrupt, is usually 1 to 2 instruction cycles depending on actual interrupt situations. INT（PA2） INTF 中断矢量 PC-1 PC+1 PC+2 0x004 0x005 Figure 27. Interrupt Response Timing Diagram Rev 1.5 | 79/91 www.cmostek.com...
  • Page 80 IOC-RA6 IOCA6 IOC-RA7 IOCA7 TMR2IF TMR2IE EEIF Interrupt EEIE To MCU CKMEAIF CKMEIE Wakeup If in sleep mode C1IF C1IE C2IF T0IF C2IE T0IE OSFIF OSFIE INTF INTE Figure 28. Interrupt Generation Circuit Block Diagram Rev 1.5 | 80/91 www.cmostek.com...

  • Page 81: Context Saving During Interrupts

    Clearing watchdog (CLRWDT) and SLEEP instruction will clear the watchdog counter. When enabled, the watchdog overflowing event can be used as a wake-up source when the MCU is in sleep mode, while it can be used as a reset source when the MCU operates normally. Rev 1.5 | 81/91 www.cmostek.com...

  • Page 82: O Port

    The mismatching result will always set the PAIF bit. Reading PORTA once can end any mismatching status to clear the PAIF bit. The last read value kept in the data register will not be affected by /MCLR or BOR. As long as the mismatching status exists, PAIF bit will set to 1. Rev 1.5 | 82/91 www.cmostek.com...

  • Page 83: Port Description

    The following figure describes The internal circuit architecture of the port is shown in the below figure. Data CLK Q /RAPU WPUA WPUA CLK Q PORTA CLK Q TRISA TRISA PORTA CLK Q IOCA PORTA IOCA Interrupt On Change T0CKI （PA2 Only） . PA<2:0> Architecture Diagram Figure 29 Rev 1.5 | 83/91 www.cmostek.com...

  • Page 84: Porta3/Pa3

    Data WPUA /RAPU WPUA PORTA ATEST1 EN TRISA TRISA PORTA IOCA PORTA IOCA Interrupt On Change Figure 30. PA3 Architecture Notes: ATEST1 is used for internal test, but not for users. Users can ignore it. Rev 1.5 | 84/91 www.cmostek.com...

  • Page 85: Porta4/Pa4

    IR MODE IR MODE ATEST0 EN TRISA TRISA PORTA IOCA PORTA IOCA Interrupt On Change Figure 31. PA4 Architecture Notes: ATEST0 and IR are used for internal test, but not for users. Users can ignore them. Rev 1.5 | 85/91 www.cmostek.com...

  • Page 86: Porta5/Pa5

    INTOSC or INTOSCIO Data CLK Q WPUA /RAPU OSC2 振荡器 电路 WPUA CLK Q PORTA CLK Q TRISA INTOSC or INTOSCIO TRISA PORTA CLK Q IOCA PORTA IOCA Interrupt On Change Figure 32. PA7 Architecture Rev 1.5 | 86/91 www.cmostek.com...

  • Page 87: Portc<7:0

    The internal circuit architecture of the port is shown in the below figure. (Only PC4) C2OUT Enable C2OUT Data PORTC Analog Input mode TRISC TRISC To Comparator PORTC (Only PC0 & PC1) Figure 33. PC7~PC0 Architecture Rev 1.5 | 87/91 www.cmostek.com...

  • Page 88: Instruction Set

    AN201 Instruction Set The CMT2189B adopts the reduced instruction set architecture with a total of 37 instructions. The instruction description is listed in the below table.. Table 90. Instruction Set Table Instruction Function Operation Status Period BCR R, b Bit clear 0->...
  • Page 89 S U B W I Subtract W from imm I-W-> W C, HC, Z Notes: The TMODE register of the chip refers to the OPTION, namely, the operation of the STTMD instruction is to save W to OPTION. Rev 1.5 | 89/91 www.cmostek.com...

  • Page 90: Revise History

    Increase the Section 2.7.1 'Tx rate description' 2017-11-29 'PC4/RFDIN”is modified as“PC0/RFDIN' 2018-01-09 Update the function description of SLVREN bit. 4.1.14, 4.1.30 2018-12-19 Change LVDEN to LVREN. Rewrite the whole EN version document 2019-03-29 Change Tx. process 2.9.2 2019-11-05 Rev 1.5 | 90/91 www.cmostek.com...

  • Page 91: Contacts

    The material contained herein is the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support devices or systems without express written approval of CMOSTEK.

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