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AN202
AN202
CMT2189C User Guideline
Summary
CMT2189C is a low power, high performance, Flash-based, (G) FSK / OOK RF transmitterchip.It can cover
the 240MHz ~ 960MHz wireless communication band. This chip is embedded with RISC Flash type MCU. It
TM
belongs to the CMOSTEK NextGenRF
series product. The product series include the short range wireless
communication chips, such as transmitter, receiver, transceiver, SoC and so on.
The part numbers covered by this document are as shown below.
Table1. Part Number Covered by This Document
Frequency
Part No.
Modem
Configuration
Package
Tx Power
Tx Current
Embedded
CMT2189C
240 - 960MHz
OOK/(G)FSK
+13dBm
32.5mA
SOP14
MCU
Note:
The test conditions for the Tx power and Tx current are at 433.92MHz and FSK mode.
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Summary of Contents for CMOSTEK CMT2189C
- Page 1 CMT2189C User Guideline Summary CMT2189C is a low power, high performance, Flash-based, (G) FSK / OOK RF transmitterchip.It can cover the 240MHz ~ 960MHz wireless communication band. This chip is embedded with RISC Flash type MCU. It belongs to the CMOSTEK NextGenRF series product.
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Page 2: Table Of Contents
CMCON0（Addr:0x19） ....................25 4.1.13 PR0（Addr:0x1A） ......................26 4.1.14 MSCKCON（Addr:0x1B） ....................26 4.1.15 SOSCPR（Addr:0x1C/0x1D） ..................27 4.1.16 OPTION（Addr:0x81） ..................... 27 4.1.17 TRISA（Addr:0x85） ......................28 4.1.18 TRISC（Addr:0x87） ......................29 4.1.19 PIE1（Addr:0x8C） ......................29 4.1.20 PCON（Addr:0x8E） ......................30 www.cmostek.com V1.0 | Page 2/73... - Page 3 Reset Timing ............................45 Power-on Reset (POR) ......................46 External Reset (MCLR) ......................46 Power-up Timer (PWRT) ......................46 Brown-out Reset (BOR（LVR）) ....................47 Error Instruction Reset ......................47 Timeout Action .......................... 47 BOOT ............................... 50 www.cmostek.com V1.0 | Page 3/73...
- Page 4 Port Description ........................66 16.3.1 PORTA<2:0> ........................66 16.3.2 PORTA5 ..........................67 16.3.3 PORTC4 and PORTC2 ..................... 69 17 Instruction Set List ..........................70 18 Document Modification Record ......................72 19 Contact Information ..........................73 www.cmostek.com V1.0 | Page 4/73...
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Page 5: Chip Architecture Introduction
1 Chip Architecture Introduction 1.1 Overall Operation Principle CMT2189C is a MCU integrated with RF transmiterchip. It uses the crystal oscillator to provide the reference frequency and digital clock for PLL, supports the OOK modulation which data rate is from 1Kbps to 30Kbps and the (G) FSK modulationwhich data rate is from 1Kbps to 100Kbps, and supports the status control based on the MCU program. -
Page 6: Io Pin Description
XTAL PC4/C2OUT/RFDAT DVDD PC2/RFCLK PA1/C1IN-/ICSPDAT PA5/MCLRB PA0/C1IN+/ICSPCLK PA2/T0CKI/INT/C1OUT Figure 1-2. CMT2189C Pin Top View Table 1-2. CMT2189C SOP14 Package Pin Description Pin No. Name Type Function Description AVDD Analog Chip RF power supply positive pole Digital Chip power supply ground... - Page 7 RF part at the same time. However, in the initialization process, MCU needs to turn off the comparator function and set its corresponding pin as the digital IO to avoid affecting the work of other functions. www.cmostek.com V1.0 | Page 7/73...
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Page 8: Rf Configuration And Control Mechanism
FSK), and from 20ms to 90ms (step unit is 10ms). 2.2 Transmitting Control Timing The RF transmitting of CMT2189C is mainly controlled by setting RFDAT (RFCLK holds the high level in the process of transmitting), and the specific timing diagram is as follows: www.cmostek.com... -
Page 9: Twi Configuration Bus（Two-Wire Interface
Figure 2-1. Transmitting Timing Diagram 2.3 TWI Configuration Bus（Two-wire Interface） CMT2189C’s internal integrated transmitting circuit is the same as CMT2119A. It supports any frequency of Sub-G ranging from 240MHz ~ 960MHz, and it also uses the TWI bus configuration interface.Through the TWI interface, users can allow CMT2189C to change the frequency(frequency hopping), transmitting power (amplitude), modulation mode (OOK, FSK, GFSK) by programming. - Page 10 Open the exp file, as shown below: Figure 2-3. Export the parameter file Configure the generation parameters to the RF of CMT2189C according to the software lookup mode, and then control the transmission according to the controlling sequence (see Section2.2).
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Page 11: Twi Timing Requirement
"0" represents the write operation. "1" represents the read operation. The latter 6-bit is the register address of the operation. The low 8-bit data is the writing value or reading value of the operation register. www.cmostek.com V1.0 | Page 11/73... -
Page 12: Twi Timing Enter And Exit
At any time, when sending a set of 0xBD01 command, RF part executes reset. After reset, RF SOFT_RST part enters the SLEEP mode directly to wait for the RFDAT edge to trigger the Tx status. www.cmostek.com V1.0 | Page 12/73... -
Page 13: Twi Configuration Process
(3) - TWI_WRREG(0x24, 0x07) (3) - TWI_WRREG(0x1A, High_data) (4) - TWI_WRREG(0x37, 0x37) (4) - TWI_WRREG(0x1D, 0x20) (4) - TWI_WRREG(0x25, 0x01) (5) - TWI_WRREG(0x38, 0x82) Step-7 Step-8 Step-9 TWI_OFF TRANSMISSION TWI_WRREG( 0x02, 0x7F) Figure 2-9. TWI Configuration Process Diagram www.cmostek.com V1.0 | Page 13/73... -
Page 14: Complete Transmission Process
(2 ) - SOFT_RST (3 ) - TWI_OFF (3 ) - TWI_OFF Figure 2-10. Configure Parameters for Each Transmission The advantage of configuring parameters for each transmission is reliable. At the same time, after completing www.cmostek.com V1.0 | Page 14/73... - Page 15 (1) - TWI_RST (1) - TWI_RST (1) - TWI_RST TRANSMISSION TRANSMISSION (2) - SOFT_RST (2) - TWI_OFF (2) - SOFT_RST (2) - TWI_OFF (2) - SOFT_RST Figure 2-12. Burning Way Transmission Process (Not configuring the register) www.cmostek.com V1.0 | Page 15/73...
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Page 16: Program Memory
0x2000~0x203F. 0x000 程序区 0x7FF 0x2000 UCFG0 0x2001 UCFG1 0x2002 UCFG2 保留 不可用 0x2010 FCFG0 0x2011 FCFG1 0x2012 FCFG2 0x2020 INFOx 0x1FFF 0x2000 信息区 0x203F 0x203F Figure 3-1. Program Space Address Mapping www.cmostek.com V1.0 | Page 16/73... -
Page 17: Special Function Register(Sfr)
- - - - 1 1 1 1 - - - - - - - - - - - - - - - - Bank0’s SRAM, which is the general RAM of 96Byte. 20-7F xxxx xxxx www.cmostek.com V1.0 | Page 17/73... -
Page 18: Bank1 Sfr
1. INDF is not a physical register. 2. The gray part is unimplemented, please do not access. 3. "-" indicates that it is unimplemented; the unimplemented register bits can not be used or written as1. It is www.cmostek.com V1.0 | Page 18/73... -
Page 19: Tmr0（Addr:0X01
Carry/ bit(ADDWF、ADDLW、SUBLW、SUBWF instructions) 1 = A carry/ from the Most Significant bit of the result occurred 0 = No carry/ from the Most Significant bit of the result occurred www.cmostek.com V1.0 | Page 19/73... -
Page 20: Porta（Addr:0X05
Type Table 4-8. PORTA Bit Function Description Name Function PORTA7 data PORTA6 data PORTA5 only acts as the input.There is no corresponding output data register. PORTA4 data PORTA3 data PORTA2 data PORTA1 data PORTA0 data www.cmostek.com V1.0 | Page 20/73... -
Page 21: Portc（Addr:0X07
1 = Enable all unmasked peripheral interrupts 0 = Disable allperipheral interrupts Timer0 Overflow Interrupt Enable bit T0IE 1 = Enable 0 = Disable PA2/INT External InterruptEnable bit INTE 1 = Enable 0 = Disable www.cmostek.com V1.0 | Page 21/73... -
Page 22: Pir1（Addr:0X0C
1 = Comparator1 output has changed 0 = Comparator1 output has not changed Oscillator FailInterrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC(must be cleared in OSFIF software) 0 = System clock runs normally www.cmostek.com V1.0 | Page 22/73... -
Page 23: Tmr2（Addr:0X11
0111 = 1:8 postscale 1000 = 1:9 postscale 1001 = 1:10 postscale 1010 = 1:11 postscale 1011 = 1:12 postscale 1100 = 1:13 postscale 1101 = 1:14 postscale 1110 = 1:15 postscale 1111 = 1:16 postscale www.cmostek.com V1.0 | Page 23/73... -
Page 24: Wdtcon（Addr:0X18
1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 11xx = 1:65536 Software Enable or Disable the watchdog timer SWDTEN 1 = WDT is turned on 0 = WDT is turned off www.cmostek.com V1.0 | Page 24/73... -
Page 25: Cmcon0（Addr:0X19
When CM[2:0]=010, 1 = C1IN+ connects to C1VIN+, C2IN+ connects to C2VIN+ 0 = C1IN- connects to C1VIN-，C2IN- connects to C2VIN- When CM[2:0]=001, 1 = C1IN+ connects to C1VIN+ 0 = C1IN- connects to C1VIN- www.cmostek.com V1.0 | Page 25/73... -
Page 26: Pr0（Addr:0X1A
SLVREN = 1 means LVR is enabled in operating mode and automatically disabled in sleep mode. SLVREN SLVREN = 0 means LVR is always enabled. 2. When LVREN is disabled in compiling option LVR is disabled regardless of SLVREN value. Reserved-bit, can not be written as 1. www.cmostek.com V1.0 | Page 26/73... -
Page 27: Soscpr（Addr:0X1C/0X1D
Low-frequency oscillator period (unit: fast clock period number) is used for slow clock 0> measurement. 4.1.16 OPTION（Addr:0x81） Table 4-29. OPTION Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OPTION /PAPU INTEDG T0CS T0SE PS<2:0> Reset Type Table 4-30. OPTION Bit Function Description Name Function www.cmostek.com V1.0 | Page 27/73... -
Page 28: Trisa（Addr:0X85
TRISA0 Reset Type Table 4-32. TRISA Bit Function Description Name Function PORTA<7:6> port direction Control bits TRISA<7:6> 1 = Input 0 = Output PORTA5 port direction Control bit TRISA<5> Only as input, fixed to 1 www.cmostek.com V1.0 | Page 28/73... -
Page 29: Trisc（Addr:0X87
0 = Disable fast clock measuring slow clock operation interrupt Comparator2 Interrupt Enable bit C2IE 1 = Enable the comparator2 interrupt 0 = Disable the comparator2 interrupt Comparator1Interrupt Enable bit C1IE 1 = Enable the comparator1 interrupt 0 = Disable the comparator1 interrupt www.cmostek.com V1.0 | Page 29/73... -
Page 30: Pcon（Addr:0X8E
Reset Type Table 4-40. OSCCONBit Function Description Name Function Internal Low Frequency OscillationMode: LFMOD 1 = 256K oscillation frequency mode 0 = 32K oscillation frequency mode Internal Oscillator Frequency Select bits IRCF<2:0> 111 = 16MHz www.cmostek.com V1.0 | Page 30/73... -
Page 31: Pr2（Addr:0X92
Timer2 cycle (comparison) register (See the Timer2 description chapter in details.) 4.1.23 WPUA（Addr:0x95） Table 4-43. WPUA Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 Reset Type www.cmostek.com V1.0 | Page 31/73... - Page 32 AN202 www.cmostek.com V1.0 | Page 32/73...
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Page 33: Ioca（Addr:0X96
Name Function CVref Enable bit VREN 1 = CVref circuit powered on 0 = CVref circuit powered down, no I drain CVref Range Select bit 1 = Low level range 0 = High level range www.cmostek.com V1.0 | Page 33/73... -
Page 34: Eedat（Addr:0X9A
0 = The write operation completed during EEPROM programming period. EEPROM Read Control bit. This bit is written only, reading will always return to 0. 1 = Initiate an EEPROM read cycle 0 = Does not initiate an EEPROM read cycle www.cmostek.com V1.0 | Page 34/73... -
Page 35: Eecon2（Addr:0X9D
1 = The PA5/MCLR pin executes the MCLR function, which is the reset pin. MCLRE 0 = The PA5/MCLR pinexecutes the PA5 function, which is the digital input pin. 1 = Disable PWRT PWRTEB 0 = Enable PWRT www.cmostek.com V1.0 | Page 35/73... - Page 36 00 = Enable the low voltage reset. Others= Disable the low voltage reset. UCFG2 address is 0x2002in PROM Table 4-59. UCFG2 Configuration Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UCFG2 LVDS<3:0> www.cmostek.com V1.0 | Page 36/73...
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Page 37: Pcl And Pclath
255 instruction, or if the lower 8-bit of memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and target location within the table. www.cmostek.com V1.0 | Page 37/73... -
Page 38: Indfand Fsr Register
0~255. Any instruction that uses the INDF register is actually access to the unit that the file selection register FSR points to. Reading the INDF indirectly will return 0. Writing the INDF indirectly will cause the control operation. (It may affect the status flag bit.) www.cmostek.com V1.0 | Page 38/73... -
Page 39: Mcu Systemclock Source
The external clock mode relies on the external circuit forthe clock source, such as the external clock EC mode, the crystal oscillator XT and LP mode. But because the related pins are not drawn out, CMT2189C can not use the external clock mode, and can only use the internal clock mode. -
Page 40: Internal Clock Mode
Hold CLKOUT to low, the clock switch circuit waits for the arrival of the falling edge oftwo new clocks. CLKOUT is now connected with the new clock, and the HTS and LTS bits of the OSCCON register are www.cmostek.com V1.0 | Page 40/73... -
Page 41: Clock Switching
Any clock switching caused by the hardware (possibly from Two-Speed Start-up or Fail-Safe Clock Monitor) will not update the SCS bit of the OSCCON register. The user should monitor the OSTS bit of the OSCCON www.cmostek.com V1.0 | Page 41/73... -
Page 42: Oscillator Start-Up Timeout Status(Osts) Bit
If the external clock oscillator is configured as any mode except the LP or XT mode, the Two-Speed Start-up will be disabled. This is because the external clock oscillation does not require any stablilization time after www.cmostek.com V1.0 | Page 42/73... -
Page 43: Two-Speed Start-Up Sequence
When the external clock fault occurs, the FSCM switches the device clock to the internal clock source, and the OSFIF flag bit of the PIR1 register is set to 1. If setting the OSFIF flag bit to 1while setting the OSFIE bit of the www.cmostek.com V1.0 | Page 43/73... -
Page 44: Fail-Safe Condition Being Cleared
(i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify whether the oscillator has successfully started and whether the system clock has been switched successfully. www.cmostek.com V1.0 | Page 44/73... -
Page 45: Reset Timing
AN202 6 Reset Timing CMT2189C has several different Resets: Power-on Reset(POR) WDT Reset during normal operation WDT Wake-up during Sleep /MCLR Reset during normal operation /MCLR Reset during Sleep Brown-out Reset（BOR/LVR） Error instruction Reset (Disable) Some registers are not affected in any Reset condition.The status of these registers is unknown on POR, and is not affected by the Reset event.Most of the other registers are restored to their "reset status"... -
Page 46: Power-On Reset (Por)
PWRT. The PWRT timing is triggered by the VDD voltage exceeding the VBOR threshold. In addition, it should be noted that the actual time varies with the conditions of temperature and voltage due to the internal slow clock drive. This time is not a precise parameter. www.cmostek.com V1.0 | Page 46/73... -
Page 47: Brown-Out Reset (Bor（Lvr）)
Power-on Reset, and the software must set it to 1 and check if it is 0. Bit1 is the /POR bit, which is 0 on Power-on Reset, and the software must set it to 1. POR_RSTN 4ms delay BOOT_EN PWRTE BOOT_END PWRT,64ms PWRT_OV MCLRB SYS_RSTN Figure 6-3. Power-on Reset with MCLRB www.cmostek.com V1.0 | Page 47/73... - Page 48 3. After the voltage is restored to normal, the internal reset will not be released immediately, but wait for about 8ms. Table 6-1. Timeout in aVariety of Cases Oscillator Power-on Reset Brown-out Reset Sleep Wake-up configuration /PWRTEB=0 /PWRTEB=1 /PWRTEB=0 /PWRTEB=1 INTOSC TPWRT TPWRT www.cmostek.com V1.0 | Page 48/73...
- Page 49 AN202 Table 6-2. STATUS/PCON Bit and Significance（U-No change，X-Unknown） /POR /BOR Condition WDT Reset WDT Wake-up /MCLR Reset during normal operation /MCLR Reset during Sleep www.cmostek.com V1.0 | Page 49/73...
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Page 50: Boot
After POR or BOR, inserting a status, the unit of EEPROM is mapped into a configuration register. The address of EEPROM starts from 2000H. The system reset is released until the end of the BOOT, as shown in Figure 6-3 and Figure 6-4. The process needs about 17us. www.cmostek.com V1.0 | Page 50/73... -
Page 51: Watchdog Timer
If the internal slow clock switches from 32K to 256K mode (or vice versa from 256K to 32K mode), it doesn't affect the watchdog timing, because WDT is fixed to use the 32K clock source. www.cmostek.com V1.0 | Page 51/73... -
Page 52: Timer0
OPTION register to enter the timer mode.When the software writes to TMR0, the timer does not increase progressively in the following 2 cycles. 9.3 Timer0 Counter Mode In this mode, the timer0 adds 1 when it is triggered by the rising or falling edge of each T0CKI pin (without www.cmostek.com V1.0 | Page 52/73... -
Page 53: Software Configuring Prescaler Circuit
When the prescaler assignment is switched from WDT to TMR0, please execute the following instruction sequence. ；Clear WDT and prescaler CLRWDT BANKSEL OPTION_REG LDWI b’11110000’；Mask TMR0 select and prescaler bits ANDWR OPTION_REG, W IORWI b’00000011’；Set prescaler to 1:16 OPTION_REG www.cmostek.com V1.0 | Page 53/73... -
Page 54: Timer0 Interrupt
Q1 and Q2 cycles of the internal clock phase, so the high level time and low level time of the external clock source cycle must meet the relevant timing requirement. www.cmostek.com V1.0 | Page 54/73... -
Page 55: Timer2
1. Both TMR2 and PR2 are read-write registers. Their values are initialized to 0 and 0xFF respectively upon Reset. 2. Setting the TMR2ON bit of the T2CON register to 1 can open Timer2, and conversely clearing the www.cmostek.com V1.0 | Page 55/73... - Page 56 5. The prescaler counter and postscaler counter will be cleared when the following register is written: Write TMR2 Write T2CON Any Reset action 6. Writing T2CON does not clear the TMR2 register. www.cmostek.com V1.0 | Page 56/73...
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Page 57: Comparator
When the word "D" is marked on the port, the user should set the corresponding TRIS bit to 0 to open the digital output driver circuit. In addition, the comparator configuration switching should mask the comparator interrupt to avoid unnecessary mistrigger events. www.cmostek.com V1.0 | Page 57/73... -
Page 58: Data Eeprom
EEDAT register.This data can therefore be read by the next instruction. EEDAT will keep this value until the user reads or writes data to the unit next time (during the write operation). BANKSEL EEADR LDWI dest_addr EEADR EECON1, RD EEDAT, W www.cmostek.com V1.0 | Page 58/73... -
Page 59: Clock Measurement
7. When the interrupt flag is checked to be 1, the read SOSCPR is the final result. CKMAVG BUS<1> CKCNTI MSCKCON WR CKMEAS EN T2 SYSCLK MEAS DONE SYSCLK TMR2 16-bit SOSCPR<11:0> To INT Figure 13-1. Slow Clock Measurement Mode Block Diagram www.cmostek.com V1.0 | Page 59/73... -
Page 60: Interrupt Mode
AN202 14 Interrupt Mode CMT2189C has the following interrupt sources: External Interrupt from PA2/INT Timer0 Overflow Interrupt PORTA ChangeInterrupt Timer2 MatchInterrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt Comparator Interrupt The Interrupt Control Register (INTCON) and the Peripheral Interrupt Request Register (PIR1) record the interrupt flag bit. -
Page 61: Porta Level Change Interrupt
The external interrupt includes the interrupt from the INT pin or the PORTA change interrupt, and the interrupt delay is usually 1 to 2 instruction cycles.It depends on the actual situation of the interrupt. INT（PA2） INTF 中断矢量 PC-1 PC+1 PC+2 0x004 0x005 Figure 14-1. Interrupt Response Timing Diagram www.cmostek.com V1.0 | Page 61/73... - Page 62 IOC-RA6 IOCA6 IOC-RA7 IOCA7 TMR2IF TMR2IE EEIF Interrupt EEIE To MCU CKMEAIF CKMEIE Wakeup If in sleep mode C1IF C1IE C2IF T0IF C2IE T0IE OSFIF OSFIE INTF INTE Figure 14-2. Interrupt Generation Circuit Block Diagram www.cmostek.com V1.0 | Page 62/73...
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Page 63: Context Saving During Interrupts
W, STATUS register, and so on.These must be implemented insoftware. The temporary registers W_TEMP and STATUS_TEMP should be placed in the last 16bytes of the GPR. The 16bytes of GPR crosses two pages, so users can save a little bit of code space. www.cmostek.com V1.0 | Page 63/73... -
Page 64: Mcu Sleep Saving Mode
Clearing watchdog (CLRWDT) and SLEEP instruction will clear the watchdog counter. When enabling the watchdog, the watchdog overflowing event can be used as a wake-up source when MCU is in Sleep, while it can be used as a reset source when MCU works normally. www.cmostek.com V1.0 | Page 64/73... -
Page 65: O Port
IOCAx register can enable or turn off the interrupts of these ports. The interrupt-on-change is invalid on Power-on Reset. When enabling the interrupt-on-change function, the current port level value is compared to the old value of www.cmostek.com V1.0 | Page 65/73... -
Page 66: Port Description
The following figure describes the internal circuit architecture of the port, and PA<2:0> can be configured as the following functional port: GPIO Debug serial clock (PA0) Debug serial data (PA1) External interrupt input (PA2) Timer0 external clock source (PA2) www.cmostek.com V1.0 | Page 66/73... -
Page 67: Porta5
Figure 16-1. PA<2:0> Architecture Block Diagram 16.3.2 PORTA5 The following figure describes the internal circuit architecture of the port, and PA5 can be configured as the following functional port: Digital Input External Reset www.cmostek.com V1.0 | Page 67/73... - Page 68 AN202 MCLRE Weak MCLRE Reset MCLRE Data TRISA PORTA CLK Q IOCA PORTA IOCA Interrupt On Change Figure 16-2. PA5 Architecture Block Diagram www.cmostek.com V1.0 | Page 68/73...
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Page 69: Portc4 And Portc2
Comparator output (only PC4, but not available, because it is used to control the RF part) (Only PC4) C2OUT Enable C2OUT Data PORTC Analog Input mode TRISC TRISC To Comparator PORTC (Only PC0 & PC1) Figure 16-3. PC4~PC0 Architecture Block Diagram www.cmostek.com V1.0 | Page 69/73... -
Page 70: Instruction Set List
AN202 17 Instruction Set List CMT2189C uses the reduced instruction set architecture with a total of 37 instructions, and the following is the description of the instructions. Table 17-1. Instruction Set Table Instruction Function Operation Status Period BCR R, b Bit clear 0->... - Page 71 Subtract W from imm I-W-> W C, HC, Z Note: The TMODE register of the chip refers to the OPTION, that is, the operation of the STTMD instruction is to save the W to OPTION. www.cmostek.com V1.0 | Page 71/73...
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Page 72: Document Modification Record
AN202 Document Modification Record Table 18-1. Document Modification Record Sheet Version Chapter Modification descriptions Date Initial release 2018-05-17 Update the function description of SLVREN bit. 4.1.14, 4.1.30 2018-12-19 Change LVDEN to LVREN. www.cmostek.com V1.0 | Page 72/73... -
Page 73: Contact Information
The material contained herein is the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support devices or systems without express written approval of CMOSTEK.
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