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AN201
AN201
CMT2189B User Guideline
Summary
CMT2189B is a low power, high performance, Flash-based, OOK RF transmitter chip.It covers the 240MHz -
960MHz wireless communication band. This chip is embedded with RISC Flash type MCU. It belongs to the
TM
CMOSTEK NextGenRF
series product.The product series includes the short range wireless communication
chips, such as transmitter, receiver, transceiver, SoC and so on.
The part numbers covered by this document are as shown below.
Table1.
Part Numbers Covered by This Document
Frequency
Part No.
Modem
Configuration
Package
Tx Power
Tx Current
Embedded
CMT2189B
240 - 960MHz
OOK
+13dBm
17.5mA
SOP14
MCU
Note: The test condition for the Tx power and Tx current is at 433.92MHz. CW mode is always in the Tx
carrier mode. The Tx current is about 8.5mA according to the Tx mode of Duty 50%.
www.cmostek.com
Copyright © By CMOSTEK
V1.2 | Page 1/92
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Summary of Contents for CMOSTEK NextGenRF CMT2189B
- Page 1 Note: The test condition for the Tx power and Tx current is at 433.92MHz. CW mode is always in the Tx carrier mode. The Tx current is about 8.5mA according to the Tx mode of Duty 50%. www.cmostek.com Copyright © By CMOSTEK V1.2 | Page 1/92...
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Page 2: Table Of Contents
Tx Process ........................30 2.10 Direct Tx Mode(Advanced Configuration Mode)............... 31 2.10.1 Power-up Initialization ....................... 31 2.10.2 Tx Process ........................31 2.10.3 Related Register ........................ 32 Program Memory ........................... 33 Special Function Register(SFR) ......................34 www.cmostek.com V1.2 | Page 2/92... - Page 3 EECON2（Addr:0x9D） ....................51 4.1.30 Configuration Register UCFGx ..................51 4.1.31 PCL and PCLATH ......................53 4.1.32 INDF and FSR Register ....................54 System Clock Source ..........................55 Clock Source Mode ........................55 External Clock Mode ......................... 56 www.cmostek.com V1.2 | Page 3/92...
- Page 4 Software Configuring Prescaler Circuit ................70 9.3.2 Timer0 Interrupt ......................... 70 9.3.3 Drive Timer0 with the External Clock ................71 10 Timer2 ..............................72 Comparator ............................. 74 12 Data EEPROM ............................75 13 Clock Measurement ..........................76 www.cmostek.com V1.2 | Page 4/92...
- Page 5 PORTA3/PA3 ........................84 16.3.3 PORTA4/PA4 ........................86 16.3.4 PORTA5/PA5 ........................87 16.3.5 PORTA7/PA7 ........................87 16.3.6 PORTC<7:0> ........................88 17 Instruction Set List ..........................89 18 Document Modification Record ......................91 19 Contact Information ..........................92 www.cmostek.com V1.2 | Page 5/92...
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Page 6: Chip Architecture Introduction
PA, and the data is modulated by OOK and transmitted out. The MCU of the chip controls the RF part by the 3-wire SPI interface, and achieves various status switching, mode selection and low power control. www.cmostek.com V1.2 | Page 6/92... -
Page 7: Io Pin Description
General IO, support IOC, can be configured as pull-up PA0/C1IN+/ICSPCLK Digital C1IN+ Comparator1 input+ Debug/ burning mode serial port Clock ICSPCLK signal General IO, support IOC, can be PA1/C1IN-/ICSPDAT Digital configured as pull-up C1IN- Comparator1 input - www.cmostek.com V1.2 | Page 7/92... - Page 8 3. PC<3:0> is the internal control pin of the chip and not the package terminal, but it is used as a bus to control the RF. www.cmostek.com V1.2 | Page 8/92...
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Page 9: Rf Configuration And Control Mechanism
(except PC1). 4. The RFCTRL pin can be suspended in this mode. 5. In this mode, the transmitted data pin is PC1(SDIO), which is set to 0 in the low power consumption www.cmostek.com V1.2 | Page 9/92... -
Page 10: Advanced Configuration Mode
3. The Direct mode which is supported by the advanced configuration mode is similar to the Direct mode of the simple work mode, by which is controlled by one data pin, but the data input source is different. In the www.cmostek.com V1.2 | Page 10/92... -
Page 11: Spi Interface Timing
SDIO needs to switch from the output state to input state before the eighth clock falling edge. > 0. 5 SCLK cycle > 0. 5 SCLK cycle RFCTRL PC3/CSB PC2/SCLK PC /SDIO r/ w = 1 register address register read data Figure 2-2. SPI Read Register Timing www.cmostek.com V1.2 | Page 11/92... -
Page 12: Rf Configuration Parameter
RFPDK software. The specific approach is to open the RFPDK software and select the CMT2157B model (the same specifications and performance as the CMT2189B built-in RF), as shown in the following figure. Figure 2-4. RFPDK CMT2157B Interface www.cmostek.com V1.2 | Page 12/92... - Page 13 Users configuration are based on the requirements according to the relevant registers below, and then click Export to generate an exp file, which is as follows: ;--------------------------------------- ; CMT2157B Configuration File ; Generated by CMOSTEK RFPDK 1.46 ; 2017.11.14 13:47 ;--------------------------------------- ; (The annotation with ";" in the middle is omitted.) ;---------------------------------------...
- Page 14 AN201 ; The following are for CMOSTEK ; use, customers can ignore them ;--------------------------------------- 0x0000 0x0018 Among them, the red font part is the specific configuration content, they are all 16-bit word, a total of 24 words, so users need to convert the 16-bit word to the 8-bit register content. The method of conversion is that the higher 8-bit of each 16-bit word is an odd number address, and the lower 8-bit is an even address.
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Page 15: Configuration Register
Bank Address Involved Content 0x00 – 0x03 Tx Bank Tx frequency,Tx power Tx rate, packet format (only for hardware packet Tx 0x04 – 0x27 Packet Bank mode） 0x28 – 0x2E System Bank System working parameters www.cmostek.com V1.2 | Page 15/92... -
Page 16: Packet Bank Register
0x0B CUS_PKT4 KEY_LENGTH<2:0> SYNC_LENGTH<4:0> 0x0C CUS_PKT5 SYNC_HEADER<7:0> 0x0D CUS_PKT6 SYNC_HEADER<15:8> 0x0E CUS_PKT7 SYNC_HEADER<23:16> 0x0F CUS_PKT8 SYNC_HEADER<31:24> 0x10 CUS_PKT9 ADDR_ID<7:0> 0x11 CUS_PKT10 ADDR_ID<15:8> 0x12 CUS_PKT11 ADDR_ID<23:16> 0x13 CUS_PKT12 ADDR_ID<31:24> 0x14 CUS_PKT13 BIT_FORMAT<2:0> ADDR_LENGTH<4:0> 0x15 CUS_PKT14 STOP_LENGTH<3:0> www.cmostek.com V1.2 | Page 16/92... -
Page 17: Tx Rate
2.7.2 Hardware Packet Format The interior of the CMT2189B supports the hardware packet structure, and its data frame structure is as follows: Head/ Stop Preamble ID/ADDR Key Value Pause/Interval Sync Status Figure 2-5. Packet Structure www.cmostek.com V1.2 | Page 17/92... -
Page 18: Preamble
2.7.3 Preamble Table 2-5. Preamble Configuration Register Register Bits Bit Name Function Description Name When enabling Tcycle, it represents the CUS_PKT1 PREAMBLE_LOCATION Preamble location in the packet structure: (0x08) 0：In one cycle, each packet contains 1 www.cmostek.com V1.2 | Page 18/92... -
Page 19: Head/Sync
Sync, and the Symbol is random in length. CUS_PKT5 SYNC_HEADER<7:0]> (0x0C) CUS_PKT6 The value of the Sync can be filled in different SYNC_HEADER<15:8> (0x0D) registersaccording to the different CUS_PKT7 SYNC_LENGTH settings, please look at the next SYNC_HEADER<23:16> table. (0x0E) CUS_PKT8 SYNC_HEADER<31:24> (0x0F) www.cmostek.com V1.2 | Page 19/92... -
Page 20: Addr/Id
Symbol, and so on, and 7 represents 8 Symbols. CUS_PKT15 BIT_LOGIC_L<7:0> Logic 0 definition (0x16) CUS_PKT16 BIT_LOGIC_H<7:0> Logic 1definition (0x17) CUS_PKT9 ADDR_ID<7:0> (0x10) CUS_PKT10 ADDR_ID<15:8> (0x11) Addr ID value CUS_PKT11 ADDR_ID<23:16> (0x12) CUS_PKT12 ADDR_ID<31:24> (0x13) www.cmostek.com V1.2 | Page 20/92... - Page 21 15, the length is 16 Logic bits, the value is 0x5678, then the user will fill the value into ADDR_ID<31:24> and ADDR_ID<23:16> registers, MSB is corresponding to the thirty-first bit, LSB is corresponding to the sixteenth bit, that is , 0x56 is filled into ADDR_ID<31:24>, 0x78 is filled into ADDR_ID<23:16>. www.cmostek.com V1.2 | Page 21/92...
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Page 22: Key Value
The Key Value length can be configured to 0~7, CUS_PKT4 and 0 represents sending the Key of 1 Logic bit, KEY_LENGTH<2:0> (0x0B) and so on, 7represents sending the Key of 8 Logic bits, and the Logic bit length is random. www.cmostek.com V1.2 | Page 22/92... -
Page 23: Lbd Status Configuration
The voltage comparison threshold of the LBD, if the actual voltage is greater than the LBD_TH<3:0> threshold, the LBD result is 1 (logic 1), and conversely, it is 0 (logic 0). CUS_LBD_RESULT LBD_RESULT<3:0> Voltage measurement value (0x4B) www.cmostek.com V1.2 | Page 23/92... - Page 24 Section 2.7.1” Packet Structure” in details. In the chip, the voltage value is converted by 4bits's ADC. The LBD_RESULT is obtained by each step of 0.2V, and the relationship between the voltage value and LBD_RESULT is as follows: www.cmostek.com V1.2 | Page 24/92...
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Page 25: Stop Bit Configuration
0 represents sending the Stop of 1 Symbol, STOP_LENGTH<3:0> (0x15) and so on, 15 represents sending the Stop of16 Symbols, and the Symbol length is random. CUS_PKT27 STOP_BIT<7:0> (0x22) STOP_BIT Value CUS_PKT28 STOP_BIT<15:8> (0x23) www.cmostek.com V1.2 | Page 25/92... -
Page 26: Pause/Interval Configuration
N data packets are transmitted repeatedly and there are Pause/Interval between the packets,or N data packets compose one group and one transmission cycle contains M groups. These ways are shown in the following figure. www.cmostek.com V1.2 | Page 26/92... - Page 27 Preamble in the packet structure. CUS_PKT1 PREAMBLE_LOCATION 0: In one cycle, each Packet contains 1 Preamble, (0x08) i.e. in one cycle, N Packets contain N Preambles. 1: In one cycle, only 1 Preamble is included, www.cmostek.com V1.2 | Page 27/92...
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Page 28: Status And Function Register
1. After executing the soft_rst, the chip is reset again, and the user needs to update the configuration register according to the requirement. 2. After power-up, the configuration register is based on the internal default value (that is, the EERPOM value burned by the factory) before the configuration register (CFG) is configured. www.cmostek.com V1.2 | Page 28/92... -
Page 29: Working Status And Status Switching
Return SLEEP status CUS_MODE Status-jump go_tx 0x02 Enter TX status （0x33） go_stby 0x08 Enter STBY status 2.8.3 Work Status Query The user needs to query the current work status by reading the CUS_STATUS (0x4D) status register, of www.cmostek.com V1.2 | Page 29/92... -
Page 30: Hardware Packet Txmode
Note: 1. When the transmission is started up again, the transmission process will be re executed. 2. In the fourth step, users need to use "read-modify-write" to avoidmodifying thevalue of other bits by www.cmostek.com V1.2 | Page 30/92... -
Page 31: Direct Tx Mode(Advanced Configuration Mode)
1. In the fifth step, the configuration register only needs to be configured as 0x00~0x03, which can adjust the Tx frequency and Tx power, and the others can be ignored. 2. When the transmission is started up again, execute the Tx process once again. www.cmostek.com V1.2 | Page 31/92... -
Page 32: Related Register
PC0 next time. So users need to think according to the encoding format. TX_OVERTIMES is 20ms by default, and can be added to 90ms that the stepping is 10ms. www.cmostek.com V1.2 | Page 32/92... -
Page 33: Program Memory
0x2000~0x203F. 0x000 程序区 0x7FF 0x2000 UCFG0 0x2001 UCFG1 0x2002 UCFG2 保留 不可用 0x2010 FCFG0 0x2011 FCFG1 0x2012 FCFG2 0x2020 INFOx 0x1FFF 0x2000 信息区 0x203F 0x203F Figure 3-1. Program Space Address Mapping www.cmostek.com V1.2 | Page 33/92... -
Page 34: Special Function Register(Sfr)
- - - - 1 1 1 1 - - - - - - - - - - - - - - - - Bank0’s SRAM, which is the general RAM of 96Bytes. 20-7F x x x x x x x x www.cmostek.com V1.2 | Page 34/92... -
Page 35: Bank1 Sfr
- - - - F0-FF Access Bank0’s 0x70～0x7F. x x x x x x x x SRAM, Note: 1. INDF is not a physical register. 2. The gray part is unimplemented, please do not access. www.cmostek.com V1.2 | Page 35/92... -
Page 36: Tmr0（Addr:0X01
Carry/ bit(ADDWF、ADDLW、SUBLW、SUBWF instructions) 1 = A carry/ from the Most Significant bit of the result occurred 0 = No carry/ from the Most Significant bit of the result occurred www.cmostek.com V1.2 | Page 36/92... -
Page 37: Porta（Addr:0X05
Type Table 4-8. PORTA Bit Function Description Name Function PORTA7 data PORTA6 data PORTA5 has only the input function.There is no corresponding output data register. PORTA4 data PORTA3 data PORTA2 data PORTA1 data PORTA0 data www.cmostek.com V1.2 | Page 37/92... -
Page 38: Portc（Addr:0X07
1 = Enable all unmasked interrupts 0 = Disable all interrupts Peripheral Interrupt Enable bit PEIE 1 = Enable all unmasked peripheral interrupts 0 = Disable allperipheral interrupts Timer0 Overflow Interrupt Enable bit T0IE 1 = Enable 0 = Disable www.cmostek.com V1.2 | Page 38/92... -
Page 39: Pir1（Addr:0X0C
Comparator2 Interrupt Flag bit C2IF 1 = Comparator2 output has changed 0 = Comparator2 output has not changed Comparator1 Interrupt Flag bit C1IF 1 = Comparator1 output has changed 0 = Comparator1 output has not changed www.cmostek.com V1.2 | Page 39/92... -
Page 40: Tmr2（Addr:0X11
0011 = 1:4 postscale 0100 = 1:5 postscale TOUTPS<3:0> 0101 = 1:6 postscale 0110 = 1:7 postscale 0111 = 1:8 postscale 1000 = 1:9 postscale 1001 = 1:10 postscale 1010 = 1:11 postscale 1011 = 1:12 postscale www.cmostek.com V1.2 | Page 40/92... -
Page 41: Wdtcon（Addr:0X18
1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 11xx = 1:65536 Software Enable or Disable the watchdog timer SWDTEN 1 = WDT is turned on 0 = WDT is turned off www.cmostek.com V1.2 | Page 41/92... -
Page 42: Cmcon0（Addr:0X19
When CM[2:0]=010, 1 = C1IN+ connects to C1VIN+, C2IN+ connects to C2VIN+ 0 = C1IN- connects to C1VIN-，C2IN- connects to C2VIN- When CM[2:0]=001, 1 = C1IN+ connects to C1VIN+ 0 = C1IN- connects to C1VIN- www.cmostek.com V1.2 | Page 42/92... -
Page 43: Pr0（Addr:0X1A
SLVREN = 1 means LVR is enabled in operating mode and automatically disabled in SLVREN sleep mode. SLVREN = 0 means LVR is always enabled. 2. When LVREN is disabled in compiling option LVR is disabled regardless of SLVREN value. www.cmostek.com V1.2 | Page 43/92... -
Page 44: Soscpr（Addr:0X1C/0X1D
Low-frequency oscillator period (unit: fast clock period number) is used for 11:0 SOSCPR<11:0> slow clock measurement. 4.1.16 OPTION（Addr:0x81） Table 4-29. OPTION Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OPTION /PAPU INTEDG T0CS T0SE PS<2:0> Reset Type www.cmostek.com V1.2 | Page 44/92... -
Page 45: Trisa（Addr:0X85
Bit3 Bit2 Bit1 Bit0 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 Reset Type Table 4-32. TRISA Bit Function Description Name Function PORTA<7:6> port direction Control bits TRISA<7:6> 1 = Input 0 = Output www.cmostek.com V1.2 | Page 45/92... -
Page 46: Trisc（Addr:0X87
1 = Enable fast clock measuring slow clock operation interrupt 0 = Disable fast clock measuring slow clock operation interrupt Comparator2 Interrupt Enable bit C2IE 1 = Enable the comparator2 interrupt 0 = Disable the comparator2 interrupt www.cmostek.com V1.2 | Page 46/92... -
Page 47: Pcon（Addr:0X8E
0 = A Brown-out Reset occured 1 = No Brown-out Reset occurred or software set it to 1. 4.1.21 OSCCON（Addr:0x8F） Table 4-39. OSCCON Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OSCCON LFMOD IRCF<2:0> OSTS Reset Type www.cmostek.com V1.2 | Page 47/92... -
Page 48: Pr2（Addr:0X92
Table 4-41. PR2 Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PR2<7:0> Reset 0xFF Type Table 4-42. PR2 Bit Function Description Name Function Timer2 period (comparison) register (See the Timer2 description chapter in PR2<7:0> details.) www.cmostek.com V1.2 | Page 48/92... -
Page 49: Wpua（Addr:0X95
Name Function Interrupt-on-change PORTA Control bit IOCA<7:0> 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled 4.1.25 VRCON（Addr:0x99） Table 4-47. VRCON Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 VRCON VREN VR<3:0> Reset Type www.cmostek.com V1.2 | Page 49/92... -
Page 50: Eedat（Addr:0X9A
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EEADR EEADR<7:0> Reset 0x00 Type 4.1.28 EECON1（Addr:0x9C） Table 4-51. EECON1 Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EECON1 WREN3 WREN2 WRERR WREN1 Reset Type www.cmostek.com V1.2 | Page 50/92... -
Page 51: Eecon2（Addr:0X9D
Write operation, 1= Initiates a data EEPROM programming cycle 0= No function 4.1.30 Configuration Register UCFGx The software does not access UCFG0, UCFG1 and UCFG2.They are only written by the hardware (burning) in the power-up process. www.cmostek.com V1.2 | Page 51/92... - Page 52 1xx = INTOSCIO mode, both PA6 and PA7 are the IO pins UCFG1address is 0x2001 in PROM Table 4-57. UCFG1 Configuration Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UCFG1 TSEL FCMEN IESO RD_CTRL LVDEN<1:0> www.cmostek.com V1.2 | Page 52/92...
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Page 53: Pcl And Pclath
PC will be cleared.The following figure shows the two situations for the loading of PC.Notice the LCALL and LJUMP instructions on the right side of the figure. Because the operating code in the instruction www.cmostek.com V1.2 | Page 53/92... -
Page 54: Indf And Fsr Register
0~255.Any instruction that uses the INDF register is actually access to the unit that the file selection register FSR points to.Reading the INDF indirectly will return 0. Writing the INDF indirectly will cause the control operation. (It may affect the status flag bit.) www.cmostek.com V1.2 | Page 54/92... -
Page 55: System Clock Source
EC mode, the crystal resonator XT and LP mode. The internal clock mode is built in the oscillator module. The oscillator module has a 16MHz high frequency oscillator and a 32KHz low frequency oscillator. www.cmostek.com V1.2 | Page 55/92... -
Page 56: External Clock Mode
Internal Oscillator Frequency Select bitI RCF<2:0> can be operated to select the system clock speed via software. The system clock can be selected between the external or internal clock source via System Clock Select bit (SCS) of the OSCCON register. www.cmostek.com V1.2 | Page 56/92... -
Page 57: Frequency Selection Bit（Ircf
4. Hold CLKOUT to low, the clock switch circuit waits for the arrival of the falling edge oftwo new clocks. 5. CLKOUT is now connected with the new clock, and the HTS and LTS bits of the OSCCON register are updated as required. 6. Clock switch is completed. www.cmostek.com V1.2 | Page 57/92... -
Page 58: Clock Switching
Any clock switching caused by the hardware (possibly from Two-Speed Start-up or Fail-Safe Clock Monitor) will not update the SCS bit of the OSCCON register.The user should monitor the OSTS bit of the OSCCON register to determine the current system clock source. www.cmostek.com V1.2 | Page 58/92... -
Page 59: Oscillator Start-Up Timeout Status(Osts) Bit
If the external clock oscillator is configured as any mode except the LP or XT mode, the Two-Speed Start-up will be disabled.This is because the external clock oscillation does not require any stablilization time after POR or an exit from Sleep. www.cmostek.com V1.2 | Page 59/92... -
Page 60: Two-Speed Start-Up Sequence
When the external clock fault occurs, the FSCM switches the device clock to the internal clock source, and the OSFIF flag bit of the PIR1 register is set to 1.If setting the OSFIF flag bit to 1while setting the OSFIE bit of the www.cmostek.com V1.2 | Page 60/92... -
Page 61: Fail-Safe Condition Being Cleared
(i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify whether the oscillator has successfully started and whether the system clock has been switched successfully. www.cmostek.com V1.2 | Page 61/92... -
Page 62: Reset Timing
6-1 and Table 6-2 in details. The /MCLRB pin corresponding circuit has the anti shake function. It can filter the sharp pulse signal caused by the interference. The following figure is the overall block diagram of the reset circuit: www.cmostek.com V1.2 | Page 62/92... -
Page 63: Power-On Reset (Por)
(such as ESD event) can result in both /MCLRB Reset and excessive current beyond the device specification. Therefore, we recommend that users no longer connect /MCLRB to VDD directly with one resistor but use the following circuit. 100R /MCLRB 0.1uF Figure 6-2. External Reset Reference Circuit Diagram www.cmostek.com V1.2 | Page 63/92... -
Page 64: Power-Up Timer (Pwrt)
/MCLR holds long enough in the low level status, the timeout event will take place. If the /MCLR is pulled up, the CPU will start immediately. This will be useful when testing or requiring multiple MCU synchronization. www.cmostek.com V1.2 | Page 64/92... - Page 65 /POR bit, which is 0 on Power-on Reset, and the software must set it to 1. POR_RSTN 4ms delay BOOT_EN PWRTE BOOT_END PWRT,64ms PWRT_OV MCLRB SYS_RSTN Figure 6-3. Power-on Reset with MCLRB POR_RSTN 4ms delay BOOT_EN PWRTE BOOT_END PWRT,64ms PWRT_OV MCLRB SYS_RSTN Figure 6-4. Power-on Reset without MCLRB www.cmostek.com V1.2 | Page 65/92...
- Page 66 Brown-out Reset Oscillator Sleep Wake-up configuration /PWRTEB=0 /PWRTEB=1 /PWRTEB=0 /PWRTEB=1 INTOSC TPWRT TPWRT Table 6-2. STATUS/PCON Bit and Significance（U-No change，X-Unknown） /POR /BOR Condition WDT Reset WDT Wake-up /MCLR Reset during normal operation /MCLR Reset during Sleep www.cmostek.com V1.2 | Page 66/92...
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Page 67: Boot
After POR or BOR, inserting a status, the unit of EEPROM is mapped into a configuration register.The address of EEPROM starts from 2000H. The system reset is released until the end of the BOOT, as shown in Figure 6-3 and Figure 6-4.The process needs about 14us. www.cmostek.com V1.2 | Page 67/92... -
Page 68: Watchdog Timer
If the internal slow clock switches from 32K to 256K mode (or vice versa from 256K to 32K mode), it doesn't affect the watchdog timing, because WDT is fixed to use the 32K clock source. www.cmostek.com V1.2 | Page 68/92... -
Page 69: Timer0
In this mode, the timer0 adds 1 when it is triggered by the rising or falling edge of each T0CKI pin (without prescaler). The T0SE bit of the OPTION register determines which edge to be triggered. The software can set the T0CS bit of OPTION register to 1 to enter the counter mode. www.cmostek.com V1.2 | Page 69/92... -
Page 70: Software Configuring Prescaler Circuit
TMR0 select and prescaler bits ANDWR OPTION_REG, W IORWI b’00000011’；Set prescaler to 1:16 OPTION_REG 9.3.2 Timer0 Interrupt An interrupt is generated (if enabling the interrupt) and the T0IF bit is set when the TMR0 timer overflows from www.cmostek.com V1.2 | Page 70/92... -
Page 71: Drive Timer0 With The External Clock
Q1 and Q2 cycles of the internal clock phase, so the high level time and low level time of the external clock source cycle must meet the relevant timing requirement. www.cmostek.com V1.2 | Page 71/92... -
Page 72: Timer2
1:1 to 1:16. The output of the Timer2 postscaler is used to set the interrupt flag bit TMR2IF of the PIR1 register to 1. Note: Both TMR2 and PR2 are read-write registers. Their values are initialized to 0 and 0xFF respectively upon www.cmostek.com V1.2 | Page 72/92... - Page 73 The Timer2 postscaler is controlled by the TOUTPS bit of the T2CON register. The prescalercounter and postscaler counter will be cleared when the following register is written: Write TMR2 Write T2CON Any Reset action Writing T2CON does not clear the TMR2 register. www.cmostek.com V1.2 | Page 73/92...
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Page 74: Comparator
When the word "D" is marked on the port, the user should set the corresponding TRIS bit to 0 to open the digital output driver circuit. In addition, the comparator configuration switching should mask the comparator interrupt to avoid unnecessary mistrigger events. www.cmostek.com V1.2 | Page 74/92... -
Page 75: Data Eeprom
EEDAT register.This data can therefore be read by the next instruction. EEDAT will keep this value until the user reads or writes data to the unit next time (during the write operation). BANKSEL EEADR LDWI dest_addr EEADR EECON1, RD EEDAT, W www.cmostek.com V1.2 | Page 75/92... -
Page 76: Clock Measurement
When the interrupt flag is checked to be 1, the read SOSCPR is the final result. CKMAVG BUS<1> CKCNTI MSCKCON WR CKMEAS EN T2 SYSCLK MEAS DONE SYSCLK TMR2 16-bit SOSCPR<11:0> To INT Figure 13-1. Slow Clock Measurement Mode Block Diagram www.cmostek.com V1.2 | Page 76/92... -
Page 77: Interrupt Mode
1 before entering the sleep status, the INT interrupt can wake up the MCU from the sleep status. Note: When INT interrupt is used, the ANSEL and CM2CON0 registers must be initialized so that the analog www.cmostek.com V1.2 | Page 77/92... -
Page 78: Porta Level Change Interrupt
The external interrupt includes the interrupt from the INT pin or the PORTA change interrupt, and the interrupt delay is usually 1 to 2 instruction cycles. It depends on the actual situation of the interrupt. INT（PA2） INTF 中断矢量 PC-1 PC+1 PC+2 0x004 0x005 Figure 14-1. Interrupt Response Timing Diagram www.cmostek.com V1.2 | Page 78/92... - Page 79 IOC-RA6 IOCA6 IOC-RA7 IOCA7 TMR2IF TMR2IE EEIF Interrupt EEIE To MCU CKMEAIF CKMEIE Wakeup If in sleep mode C1IF C1IE C2IF T0IF C2IE T0IE OSFIF OSFIE INTF INTE Figure 14-2. Interrupt Generation Circuit Block Diagram www.cmostek.com V1.2 | Page 79/92...
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Page 80: Context Saving During Interrupts
The temporary registers W_TEMP and STATUS_TEMP should be placed in the last 16 Bytes of the GPR.The 16 Bytes of GPR cross two pages, so users can save a little bit of code space. www.cmostek.com V1.2 | Page 80/92... -
Page 81: Mcu Sleep Saving Mode
Clearing watchdog (CLRWDT) and SLEEP instruction will clear the watchdog counter. When enabling the watchdog, the watchdog overflowing event can be used as a wake-up source when MCU is in Sleep, while it can be used as a reset source when MCU works normally. www.cmostek.com V1.2 | Page 81/92... -
Page 82: O Port
Each port of the PORTA can be separately set as an interrupt source (interrupt-on-change). Controlling the bitof the IOCAx register can enable or turn off the interrupts of these ports. The interrupt-on-change is invalid on Power-on Reset. www.cmostek.com V1.2 | Page 82/92... -
Page 83: Port Description
The following figure describes the internal circuit architecture of the port, and PA<2:0> can be configured as the following functional port: GPIO Debug serial clock (PA0) Debug serial data (PA1) External interrupt input (PA2) Timer0 external clock source (PA2) www.cmostek.com V1.2 | Page 83/92... -
Page 84: Porta3/Pa3
On Change T0CKI （PA2 Only） Figure 16-1. PA<2:0> Architecture Block Diagram 16.3.2 PORTA3/PA3 The following figure describes the internal circuit architecture of the port, and PA3 can be configured as the following functional port: GPIO www.cmostek.com V1.2 | Page 84/92... - Page 85 PORTA ATEST1 EN TRISA TRISA PORTA IOCA PORTA IOCA Interrupt On Change Figure 16-2. PA3 Architecture Block Diagram Note: ATEST1 is used for the internal test, not open to users, and users can ignore it. www.cmostek.com V1.2 | Page 85/92...
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Page 86: Porta4/Pa4
ATEST0 EN TRISA TRISA PORTA IOCA PORTA IOCA Interrupt On Change Figure 16-3. PA4 Architecture Block Diagram Note: ATEST0 and IR are used for the internal test, not open to users, and users can ignore them. www.cmostek.com V1.2 | Page 86/92... -
Page 87: Porta5/Pa5
INTOSCIO Data CLK Q WPUA /RAPU OSC2 振荡器 电路 WPUA CLK Q PORTA CLK Q TRISA INTOSC or INTOSCIO TRISA PORTA CLK Q IOCA PORTA IOCA Interrupt On Change Figure 16-4. PA7 Architecture Block Diagram www.cmostek.com V1.2 | Page 87/92... -
Page 88: Portc<7:0
Comparator output (only PC4, but not available, because it is used to control the RF part) (Only PC4) C2OUT Enable C2OUT Data PORTC Analog Input mode TRISC TRISC To Comparator PORTC (Only PC0 & PC1) Figure 16-5. PC7~PC0 Architecture Block Diagram www.cmostek.com V1.2 | Page 88/92... -
Page 89: Instruction Set List
Load immediate to W I-> W NONE A N DW I AND W and imm W& I-> W IORW I Inclu.OR W and imm W| I-> W X O RW I Exclu.OR W and imm W^ I-> W www.cmostek.com V1.2 | Page 89/92... - Page 90 Subtract W from imm I-W-> W C, HC, Z Note: The TMODE register of the chip refers to the OPTION, that is, the operation of the STTMD instruction is to save the W to OPTION. www.cmostek.com V1.2 | Page 90/92...
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Page 91: Document Modification Record
Table 18-1. Document Modification Record Sheet Versio Chapter Modification descriptions Date Initial release 2017-11-23 Increase the Section 2.7.1 “Tx rate description” 2017-11-29 “PC4/RFDIN”is modified as“PC0/RFDIN” 2018-01-09 Update the function description of SLVREN bit. 4.1.14, 4.1.30 2018-12-19 Change LVDEN to LVREN. www.cmostek.com V1.2 | Page 91/92... -
Page 92: Contact Information
The material contained herein is the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support devices or systems without express written approval of CMOSTEK.
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