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5
Filter
Filter Constant sets the level of digital filtering according to
the following chart.
0
1
2
3
4
5
100
90
80
70
60
50
40
30
20
10
0
0
20
40
Digital Filtering. The illustration above demonstrates the
effect of digital filtering (set with Filter
Constant) on module response to a
temperature change.
6
I/O Register Map
Registers
%I1 to %I24
%I32
%I25 to %I31
%Q1 to %Q16
%Q17
Clear HSC1 accumulator to 0
Totalizer: Clear HSC2
%Q18
Quadrature 1-2: Accumulator 1
Reset to max – 1
%Q19
Clear HSC3 Accumulator to 0
Totalizer: Clear HSC4
%Q20
Quadrature 3-4: Accumulator 3
Reset to max – 1
%Q21 to %Q32
%AI1 to %AI4
%AI5, %AI6
HSC1 Accumulator
%AI7, %AI8
HSC2 Accumulator
%AI9, %AI10
HSC3 Accumulator
%AI11, %AI12
HSC4 Accumulator
%AQ1, %AQ2
PWM1 Duty Cycle
%AQ3, %AQ4
PWM2 Duty Cycle
%AQ5, %AQ6
%AQ7, %AQ8
%AQ9 to %AQ14
Analog outputs
Note: Not all XLe units contain the I/O listed in this table.
Registers
PWM
%AQ1
PWM1 Duty
Cycle
(32 bit)
%AQ2
PWM2 Duty
%AQ3
Cycle
%AQ4
(32 bit)
%AQ5
PWM Prescale
%AQ6
(32 bit)
%AQ7
PWM Period
(32 bit)
%AQ8
%Q1
%I30
%I31
__________________________________________________________________________________________________________________________________________________________________
Filter
6
7
Constant
60
80
100
Scans
7
Description
Digital Inputs
Output Fault
Reserved
Digital outputs
Reserved
Analog inputs
PWM Prescale
PWM Period
HSC
Stepper
Start
HSC1
Frequency
Preset
Run
Value
Frequency
HSC2
Accel Count
Preset
(32 bit)
Value
Run Count
(32 bit)
Decel Count
(32 bit)
Run
Ready/Done
Error
MJ2 Pinouts in Full and Half Duplex Modes
Pin
MJ2 Pins
8
Signal
Direction
8
TXD
OUT
7
RXD
IN
1
6
0 V
Ground
5*
+5 60mA
OUT
4
TX-
OUT
3
TX+
OUT
2
RX-
IN
1
RX+
IN
* +5 on XLe Rev E and later
Full Duplex Mode
Pin
MJ2 Pins
8
Signal
Direction
8
TXD
OUT
7
RXD
IN
1
6
0 V
Ground
5*
+5 60mA
OUT
4
TX-
OUT
3
TX+
OUT
2
TX-/RX-
IN/OUT
1
TX+/RX+
IN/OUT
* +5 on XLe Rev E and later
Half Duplex Mode
Page 3 of 4
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