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3-5-4 Processor and Memory Module Matrix Table
Memory Q'ty
for each CPU
B0
A0
1 DIMM
V
2 DIMM
V
4 DIMM
V
6 DIMM
V
V
8 DIMM
V
V
NOTE!
l There should be at least one DDR4 DIMM per socket.
l If only one DIMM is populated in a channel, then populate it in the slot furthest away from CPU of that channel.
l Channel 0's on each memory controller (A/E/C/G, I/M/K/O) must be populated with same total capacity per channel
(if populated).
l Channel 1's on each memory controller (B/F/D/H, J/N/L/P) must be populated with same total capacity per channel
(if populated).
CPU0
D0
C0
G0
H0
V
V
V
V
V
V
V
V
System Hardware Installation
E0
F0
J0
I0
L0
V
V
V
V
V
V
V
V
V
V
V
V
V
- 30 -
CPU1
K0
O0
P0
M0
V
V
V
V
V
V
V
V
N0
V
V
V
V
V
V
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