74Lvc14A; Description; Features; Pinning - Hitachi 32LD8700C Service Manual

For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
11.7.

74LVC14A

11.7.1.

Description

The 74LVC14A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5V devices. This
feature allows the use of these devices as translators in a mixed 3.3 and 5V environment. The
74LVC14A provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
11.7.2.

Features

• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no.8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
• Specified from -40 to +85C and -40 to +125C.
11.7.3.

Pinning

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