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Toshiba TC32306FTG Manual page 73

Single-chip rf transceiver for low-power systems

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6.10.20 h'1C Peak Hold Settings
D7
Name
Peak_Ref2
Peak_Ref1
Initial
1
Type
R/W
[D7:D5] Peak_Ref2..0 [Limiter (Peak Hold Voltage Discharge Coefficient)]
When to set ASK Demodulation (h'0A[D4]FSK_ASK = "1") and Data Comparator Quick Charge 2 (h'10[D6]Charge2_en = "1"),
this setting is valid. Set the discharge time constant of Peak Hold circuit.
Discharge time constant τ: τ = tr / fbc
tr: Setting value of this register:Peak_Ref2..0 (Refer to the table below.)
fbc: Internal clock signal frequency depends on Bit Rate Filter register:h'0E [D4:D1]BRF_Bit3..0
[D7]Peak_Ref2
[D6]Peak_Ref1
0
0
0
0
1
1
1
1
See section 6.5.7 about Peak Hold circuit.
Notice: The cutoff frequency of Bit Rate Filter is derived from 30.32MHz Reference Clock Frequency.
[D4:D3] Peak_Charge1..0 [Limiter (Peak Hold Voltage Charge Coefficient)]
When to set ASK Demodulation (h'0A[D4]FSK_ASK = "1") and Data Comparator Quick Charge 2 (h'10[D6]Charge2_en = "1"),
this setting is valid. Set the charging time constant peak tracking of Peak Hold circuit.
Charge time constant peak tracking τ: τ = tp' / fbc
tp': Inverse of "(1/tp)+(1/tr)"
tp: Setting value of this register:Peak_Charge1..0 (Refer to the table below.)
tr: Setting value of this register:Peak_Ref2..0
fbc: Internal clock signal frequency depends on Bit Rate Filter register:h'0E [D4:D1]BRF_Bit3..0
[D4]Peak_
[D3]Peak_
Charge1
Charge0
0
0
1
1
See section 6.5.7 about Peak Hold circuit.
Notice: The cutoff frequency of Bit Rate Filter is derived from 30.32MHz Reference Clock Frequency.
[D2 ]NIR_2L0
When to use NIR filter (h'10[D1]NIR_Fil_en = "1") and Delay Detection (h'10[D0]Sel_Det = "0"), set this register "0".
When to use NIR filter (h'10[D1]NIR_Fil_en = "1") and Pulse Count Detection (h'10[D0]Sel_Det = "1"), set this register "1".
Table 6-75 Register (h'1C)
D6
D5
Peak_
Peak_Ref0
Charge1
0
0
R/W
R/W
[D5]Peak_Ref0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1/tp
0
1/8
1
1/16
0
1/32
1
1/64
D4
D3
Peak_
NIR_2L0
Charge0
0
1
R/W
R/W
1/tr
tr
1/64
64
1/128+1/256
85.3
1/128
128
1/256+1/512
170.7
1/256
256
1/512+1/1024
341.3
1/512
512
1/1024+1/2048
682.7
tp
8
16
32
64
73
TC32306FTG
D2
D1
D0
NIR_L1
NIR_L0
0
0
R/W
R/W
R/W
2015-10-01
0

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