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between EEPROM address and the register address of this IC are shown in Table 6-40.
6.7.8
EEPROM Control Data Format
In EEPROM Mode, TC32306FTG operates Burst Read for the EEPROM. The configuration is selected
by the combination of TX_SW pin, RX_SW pin and ENB pin.
Notice:
- The memory size of 1 k, 2 k and 4 k bit are available for EEPROM. The configuration of 2,4 and 8 are
available respectively.
- Select EEPROM adapted for Burst Read.
- The serial clock (= CLK pin output signal) to read EEPROM data generated by the inner oscillator of
TC32306FTG is frequency of about 2 MHz. Select EEPROM adapted for that frequency.
(1)
Set the configuration with TX_SW pin, RX_SW pin and ENB pin from MCU. Then set RESET pin is
"H". (= The reset is released.) The configuration change is available all the time, however the
operation is valid at the timing of change of RESET pin from "L" to "H".
(2)
TC32306FTG operates Burst Read to the first set data area of EEPROM through SPI lines. Burst
Read operates from the start address till the end address of the configuration data sequentially. After
the reading, this IC starts to Run as the configuration of first set data area.
(3)
This IC operates Burst Read to the second and third set data area continuously, then the register
setting is fixed by majority logic.
(4)
This IC runs depending on the register:h'0A[D6]ACT.
MOSI
Instruction Address
MISO
Instruction
0 0 0 0
X
0
MOSI
X： "0" at EEPROM Address < 256, "1" at EEPROM Address ≥ 256
MISO
CLK
CS
Fig 6-24 Read Format from EEPROM (EEPROM Mode)
N
N+1
Read
Read
Read
Data
Data
Address
1 1
Don't care
- - -
N+2
N+3
Read
- - -
Data
Data
Low
Read Data
Read Data
40
TC32306FTG
Read
Read
Data
Data
Low
- - -
- - -
- - -
- - -
2015-10-01
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