Advertisement
Table 6-41 EEPROM Mode Timing (COM_VDD = 3.0 - 5.5V)
CLK Frequency *
CLK Rising Time *
CLK Falling Time *
CLK Delay Time *
CS Delay Time *
MOSI Preceding Time *
MOSI Delay Time *
MISO Delay Time
MISO Setup Time
MISO Hold Time
* Time values of CLK, MISO and MOSI are derived at the load capacitance of 10pF.
Table 6-42 EEPROM Mode Timing (COM_VDD = 2.5 - 3.0V)
CLK Frequency *
CLK Rising Time *
CLK Falling Time *
CLK Delay Time *
CS Delay Time *
MOSI Preceding Time *
MOSI Delay Time *
MISO Delay Time
MISO Setup Time
MISO Hold Time
* Time values of CLK, MISO and MOSI are derived at the load capacitance of 10pF.
6.8 User Test
This is a mode to monitor internal digital signal for design, development, manufacturing or shipping
inspection. Set MODE1 pin to be "H" and/or the register: USER_TEST bit is "1" then TC32306FTG moves to
User Test. In User Test, various internal signals for the adjustment are converted to analog and are output
from DET_TMONI3 pin or DET_TMONI4 pin by the setting of register. The way of setting register of SPI
Mode is different from that of EEPROM Mode.
Item
Code
f
ck
CLK "H" Time *
t
CKWH
CLK "L" Time *
t
CKWL
t
CKR
t
CKF
t
CKD
t
CSD
CS "H" Time *
t
CSWH
CS Hold Time *
t
CSH
t
MOS
t
MOD
t
MID
t
MIS
t
MIH
Item
Code
f
ck
CLK "H" Time *
t
CKWH
CLK "L" Time *
t
CKWL
t
CKR
t
CKF
t
CKD
t
CSD
CS "H" Time *
t
CSWH
CS Hold Time *
t
CSH
t
MOS
t
MOD
t
MID
t
MIS
t
MIH
Min
Typ.
Max
1.0
2.0
3.0
125
-
-
125
-
-
50
-
-
50
-
-
150
-
-
400
-
-
500
-
-
100
-
-
-
-
50
-
-
50
90
-
-
10
-
-
100
-
-
Min
Typ.
Max
1.0
2.0
3.0
150
-
-
150
-
-
50
-
-
50
-
-
150
-
-
400
-
-
500
-
-
100
-
-
-
-
50
-
-
50
120
-
-
10
-
-
100
-
-
43
TC32306FTG
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2015-10-01
Advertisement
